37.7.48 USB LPM Interrupts Status Register

Table 37-50. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	LPMINTR
Offset:	0x1364
Reset:	0x0000
Property:	PAC Write-Protection


Bit	7	6	5	4	3	2	1	0
			LPMERR	LPMRES	LPMNC	LPMACK	LPMNY	LPMST
Access			R	R	R	R	R	R
Reset			0	0	0	0	0	0

Bit 5 – LPMERR LPM Error Interrupt Flag bit

Device Mode only bit. Unimplemented in Host mode.

Value	Description
0	No error condition
1	An LPM transaction was received that had a LINKSTATE field that is not supported. The response will be a STALL.

Bit 4 – LPMRES LPM Resume Interrupt Flag bit

This bit is mutually exclusive from the RESUME bit in the Power register.

Value	Description
0	No Resume condition
1	The USB module has resumed (for any reason)

Bit 3 – LPMNC LPM Not Complete Interrupt Flag bit

When in Device mode:

1= The USB module received an LPM transaction and responded with a NYET due to data pending in the RX FIFOs.

0 = No NC interrupt condition

When in Host mode:

1= An LPM transaction is transmitted and has failed to complete. The transaction will have failed because a timeout occurred or there were bit errors in the response for three attempts.

0 = No NC interrupt condition