37.7.46 USB LPM Control Register

Table 37-48. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	LPMCNTRL
Offset:	0x1362
Reset:	0x0000
Property:	PAC Write-Protection


Bit	7	6	5	4	3	2	1	0
				LPMNAK	LPMEN[1:0]		LPMRES	LPMXMT
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bit 4 – LPMNAK LPM-only Transaction Setting bit

Device Mode only bit. Unimplemented in Host mode.

This bit is used to place all end points in a state such that the response to all transactions other than an LPM transaction will be a NAK.

Setting this bit to '1'will only take effect after the USB module has been LPM suspended. In this case, the USB device will continue to NAK until this bit has been cleared by software.

Value	Description
0	Normal transaction operation
1	All endpoints will respond to all transactions other than an LPM transaction with a NAK

Bits 3:2 – LPMEN[1:0] LPM Enable bits

Device Mode only bit. Unimplemented in Host mode.

Value	Description
11	LPM Extended transactions are supported
10	LPM and Extended transactions are not supported
01	LPM mode is not supported but Extended transactions are supported
00	LPM Extended transactions are supported

Bit 1 – LPMRES LPM Resume bit

When in Device mode:

This bit is used by software to initiate resume (remote wakeup). This bit differs from the classic RESUME bit in the POWER register (address offset 0x0001) in that the RESUME signal timing is controlled by hardware. When software writes this bit, resume signaling will be asserted for 50us. This bit is self-clearing.

1 = Initiate resume (remote wake-up). Resume signaling is asserted for 50 µs.

0 = No resume operation

This bit is self-clearing.

When in Host mode:

This bit is used by software to initiate a RESUME from the L1 State. This bit differs from the classic RESUME bit in the POWER register (address offset 0x0001) in that the RESUME signal timing is controlled by hardware. When software writes this bit, resume signaling will be asserted for a time specified by the HIRD field in the LPMATTR register.

1 = Initiate resume

0 = No resume operation

This bit is self-clearing.

Bit 0 – LPMXMT LPM Transition to the L1 State bit

When in Device mode:

1 = USB module will transition to the L1 state upon the receipt of the next LPM transaction. LPMEN must be set to ‘0b11. Both LPMXMT and LPMEN must be set in the same cycle.

0 = Maintain current state

When LPMXMT and LPMEN are set, the USB module can respond in the following ways:

If no data is pending (all TX FIFOs are empty), the USB module will respond with an ACK. The bit will self-clear and a software interrupt will be generated.
If data is pending (data resides in at least one TX FIFO), the USB module will respond with a NYET. In this case, the bit will not self-clear however a software interrupt will be generated.