37.7.28 USB RX FIFO Size Register

RXFIFOSZ controls the size of the selected RX endpoint FIFO.

Table 37-30. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: RXFIFOSZ
Offset: 0x1063
Reset: 0x0000
Property: PAC Write-Protection

Bit 76543210 
    DPBFIFOSZ[3:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bit 4 – DPB RX Endpoint Double-packet Buffering Control bit

ValueDescription
0Double-packet buffer is not supported
1Double-packet buffer is supported. This doubles the size set in RXFIFOSZ.

Bits 3:0 – FIFOSZ[3:0] RX Endpoint FIFO packet size bits

The maximum packet size to allowed for (before any splitting within the FIFO of Bulk/High-Bandwidth packets prior to transmission)

ValueDescription
1111Reserved
1010Reserved
10014096 bytes
10002048 bytes
01111024 bytes
0110512 bytes
0101256 bytes
0100128 bytes
001164 bytes
001032 bytes
000116 bytes
00008 bytes