37.7.11 USB RX Interrupt Flag Register
Note: Interrupt flags must be cleared and then read back to confirm the clear before
exiting the ISR to avoid double interrupts.
All EPnRX and are cleared when this register is read. Therefore, each bit must be read independently from the remaining bits in this register to avoid accidental clearing.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTRRX |
| Offset: | 0x1004 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EP6RXIF | EP5RXIF | EP4RXIF | EP3RXIF | EP2RXIF | EP1RXIF | EP0RXIF | |||
| Access | R/HS | R/HS | R/HS | R/HS | R/HS | R/HS | R/HS | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 1, 2, 3, 4, 5, 6, 7 – EPnRXIF Endpoint ‘n’ RX Interrupt Flag bit
| Value | Description |
|---|---|
| 0 | No interrupt event |
| 1 | Endpoint has a transmit interrupt to be serviced |