37.7.45 USB LPM Attribute Register for LPM Transaction and Sleep Cycle
This register is used to define the attributes of an LPM transaction and sleep cycle. In both the Host mode and the Device mode, the meaning of this register is the same however the source of the data is different for Host and Device as follows:
In Device mode:
In Device mode, the values in this register will contain the equivalent attributes that were received in the last LPM transaction that was accepted. This register is updated with the LPM packet contents if the response to the LPM transaction was an ACK. This register can be update via software. In all other cases, this register will hold its current value.
In Host mode:
In Host mode software will set-up the values in this register to define the next LPM transaction that will be transmitted. These values will be inserted in the payload of the next LPM Transaction.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | LPMATTR |
| Offset: | 0x1360 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ENDPOINT[3:0] | RMTWAK | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HIRD[3:0] | LNKSTATE[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:12 – ENDPOINT[3:0] LPM Token Packet Endpoint bits
This is the endpoint in the token packet of the LPM transaction.
Bit 8 – RMTWAK Remote Wake-up Enable bit
This bit is applied on a temporary basis only and is only applied to the current suspend state. After the suspend cycle, the remote wakeup capability that was negotiated upon enumeration applies.
| Value | Description |
|---|---|
| 0 | Remote wake-up is disabled |
| 1 | Remote wake-up is enabled |
Bits 7:4 – HIRD[3:0] Host Initiated Resume Duration bits
The minimum time the host will drive resume on the bus. The value in this register corresponds to an actual resume time of:
Resume Time = 50 µs + HIRD * 75 µs. The resulting range is 50 µs to 1200 µs.
Bits 3:0 – LNKSTATE[3:0] Link State bits
This value is provided by the host to the peripheral to indicate what state the
peripheral must transition to after the receipt and acceptance of an LPM
transaction. The only valid value for this register is '1' for
Sleep State (L1). All other values are reserved.