37.7.10 USB TX Interrupt Flag Register
Note: Interrupt flags must be cleared and then read back to confirm the clear before
exiting the ISR to avoid double interrupts.
All EPnTX and EP0 bits are cleared when this register is read. Therefore, each bit must be read independently from the remaining bits in this register to avoid accidental clearing.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTRTX |
| Offset: | 0x1002 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EP6TXIF | EP5TXIF | EP4TXIF | EP3TXIF | EP2TXIF | EP1TXIF | EP0TXIF | EP0IF | ||
| Access | R/HS | R/HS | R/HS | R/HS | R/HS | R/HS | R/HS | R/HS | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 1, 2, 3, 4, 5, 6, 7 – EPnTXIF Endpoint ‘n’ TX Interrupt Flag bit
| Value | Description |
|---|---|
| 0 | No interrupt event |
| 1 | Endpoint has a transmit interrupt to be serviced |
Bit 0 – EP0IF Endpoint 0 Interrupt bit
| Value | Description |
|---|---|
| 0 | No interrupt event |
| 1 | Endpoint 0 has an interrupt to be serviced |