37.7.1 Control A Register
Note: All bits in CTRLA are enable protected except for ENABLE and SWRST.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLA |
| Offset: | 0x0000 |
| Reset: | 0x0000000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| REFCLKSEL | IDOVEN | IDVAL | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ENABLE | SWRST | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 10 – REFCLKSEL Select USB PLL Reference Clock Speed
| Value | Description |
|---|---|
| 0 | 12 MHz clock input |
| 1 | 24 MHz clock input |
Bit 9 – IDOVEN ID Source Select
Note: Affects the value of DEVCTL.B Device.
| Value | Description |
|---|---|
| 0 | IDDIG value from PHY is the source of ID |
| 1 | IDVAL is the source of ID |
Bit 8 – IDVAL Override value of ID
| Value | Description |
|---|---|
| 0 | ID override value is 0 (A plug) bit |
| 1 | ID override value is 1 (B plug) |
Bit 1 – ENABLE Enable
Note:
- Due to synchronization, there is delay from writing CTRLA.ENABLE until the operation completes. The value written to CTRL.ENABLE reads back immediately and the SYNCBUSY.ENABLE bit is set. SYNC- BUSY.ENABLE is cleared when the operation completes.
- Before clearing ENABLE ensure the USBCORE Controller has entered Suspend mode.
- It is necessary to make all other configuration settings in this register first before setting the ENABLE bit.
| Value | Description |
|---|---|
| 0 | Disable module: Only SFR reads/writes |
| 1 | Enable module: Requests Reference Clock |
Bit 0 – SWRST Software initiated Reset for USB System
Note:
- Writing'1' to CTRLA.SWRST take precedence over other bit updates in the same write-operation. Any register write during the ongoing reset results in a bus error. Reading any register returns the reset value of the register.
- Due to synchronization there is a delay from writing CTRLA.SWRST until the reset completes. CTRLA.SWRST and SYNCBUSY.SWRST are both cleared when the reset is completes.
- During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST is cleared by hardware.
| Value | Description |
|---|---|
| 0 | This module remains in its current state. Writing a 0 to this field has no effect. |
| 1 | Reset all logic and registers in the USB system, except SYNCBUSY.SWRST, and disable the module (USBCORE, PHY, and VREG). |