This register identifies the current memory address of the corresponding DMA channel.
The initial memory address written to this register during initialization must have
a value such that its modulo 4 value is equal to '0'. The lower two
bits of this register are read only and cannot be set by software. As the DMA
transfer progresses, the memory address will increment as bytes are transferred.
Table 37-42. Register Bit Attribute
Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable bit
HC
Cleared by Hardware
(Grey cell)
Unimplemented
W
Writable bit
HS
Set by Hardware
X
Bit is unknown at Reset
K
Write to clear
S
Software settable bit
—
—
Name:
DMAxADDR
Offset:
0x1208 + x*0x0A [x=0..7]
Reset:
0x0000000000
Property:
PAC
Write-Protection
Bit
31
30
29
28
27
26
25
24
DMAADDR[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DMAADDR[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DMAADDR[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DMAADDR[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – DMAADDR[31:0] DMA Memory Address bits
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