PIC32CZ CA80/CA90 Family

37.7.15 USB Interrupt Enable Register

Table 37-17. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	INTRUSBE
Offset:	0x100B
Reset:	0x0000
Property:	PAC Write-Protection


Bit	7	6	5	4	3	2	1	0
	VBUSERREN	SESSREQEN	DISCONEN	CONNEN	SOFEN	RESETEN	RESUMEEN	SUSPENDEN
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	1	0

Bit 7 – VBUSERREN VBUS Error Interrupt Enable Bit

Value	Description
0	V_BUS error interrupt is disabled
1	V_BUS error interrupt is enabled

Bit 6 – SESSREQEN Session Request Interrupt Enable bit

Value	Description
0	Session request interrupt is disabled
1	Session request interrupt is enabled

Bit 5 – DISCONEN Device Disconnect Interrupt Enable bit

Value	Description
0	Device disconnect interrupt is disabled
1	Device disconnect interrupt is enabled

Bit 4 – CONNEN Device Connection Interrupt Enable bit

Value	Description
0	Device connection interrupt is disabled
1	Device connection interrupt is enabled

Bit 3 – SOFEN Start of Frame Interrupt Enable bit

Value	Description
0	Start of Frame event interrupt is disabled
1	Start of Frame event interrupt is enabled

Bit 2 – RESETEN Reset/Babble Interrupt Enable bit

Value	Description
0	Reset/Babble interrupt is disabled
1	Interrupt when reset (Device mode) or Babble (Host mode) is enabled

Bit 1 – RESUMEEN Resume Interrupt Enable bit

Value	Description
0	Resume signaling interrupt is disabled
1	Resume signaling interrupt is enabled

Bit 0 – SUSPENDEN Suspend Interrupt Enable bit

Value	Description
0	Suspend signaling interrupt is disabled
1	Suspend signaling interrupt is enabled

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