42.7.12 ADCn Event Control (ADC)
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | EVCTRL[n] |
| Offset: | 0x3C + n*0x20 [n=0..3] |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protected, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CMPEO | RESRDYEO | STARTINV | STARTEI | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 5 – CMPEO Window Event Out Enable
This bit indicates whether the Digital Comparator Window event output is enabled or not and whether an output event will be generated when the Digital Comparator Window is met.
Note: These events correspond to
EVSYS Event Generators 127-130 for Modules 0-3.
Note:
- This bit is Enabled Protected. (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)
| Value | Description |
|---|---|
| 0 | Window event output is disabled, and an event will not be generated. |
| 1 | Window event output is enabled, and an event will be generated. |
Bit 4 – RESRDYEO Result Ready Event Out Enable
This bit indicates whether the Result Ready event output is enabled or not and an output event will be generated when the conversion result is available.
Note: These events correspond to
EVSYS Event Generators 123-126 for Modules 0-3.
Note:
- This bit is Enabled Protected. (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)
| Value | Description |
|---|---|
| 0 | Result Ready event output is disabled, and an event will not be generated. |
| 1 | Result Ready event output is enabled, and an event will be generated. |
Bit 3 – STARTINV Start Sample/Conversion Event/Trigger Invert Enable
Note:
- Only rising edge EVSYS ADC Trigger events are acknowledged.
- This bit is Enabled Protected. (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error).
| Value | Description |
|---|---|
| 0 | Start event input source is not inverted. |
| 1 | Start event input source is inverted. |
Bit 0 – STARTEI Start Conversion Event/Trigger Enable
Note:
- This bit is Enabled Protected. (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)
| Value | Description |
|---|---|
| 0 | Not enabled. ADC Event System events cannot trigger start of conversions. |
| 1 | Enabled. ADC Event System events can trigger start of conversions. |