42.7.21 ADC3 Channel Configuration Registers 1 (ADC)
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CONFIG[3].CHNCFG1 |
| Offset: | 0x84 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protected, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| LVL6 | LVL5 | LVL4 | LVL3 | LVL2 | LVL1 | LVL0 | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHNCMPE6 | CHNCMPE5 | CHNCMPE4 | CHNCMPE3 | CHNCMPE2 | CHNCMPE1 | CHNCMPE0 | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 16, 17, 18, 19, 20, 21, 22 – LVLk Trigger Level for Input k
Bit 22 :LVL6 Scan Level Trigger mode select for ADC Module 3, analog internal IVREF 1.2V
Bit 21 :LVL5 Scan Level Trigger mode select for ADC Module 3, analog input ADC3_AIN5
Bit 20 :LVL4 Scan Level Trigger mode select for ADC Module 3, analog input ADC3_AIN4
Bit 19 :LVL3 Scan Level Trigger mode select for ADC Module 3, analog input ADC3_AIN3
Bit 18 :LVL2 Scan Level Trigger mode select for ADC Module 3, analog input ADC3_AIN2
Bit 17 :LVL1 Scan Level Trigger mode select for ADC Module 3, analog input ADC3_AIN1
Bit 16 :LVL0 Scan Level Trigger mode select for ADC Module 3, analog input ADC3_AIN0
- These bits are ignored if CTRLB.SWCNVEN = 1 and CTRLB.ADCORSEL = 0.
- These bits are Enabled Protected (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error).
| Value | Description |
|---|---|
| 0 | Rising edge scan trigger mode select. A rising edge trigger event will initiate a single but complete scan of all included scan channels defined in CHNCFG23.CSSy. (Default) |
| 1 | Level scan trigger mode select. As long as the trigger event stays a logic high when the corresponding CHNCFG43 TRGSRCx = 0b0011, (SCANTRG - Scan Trigger Select), the entire scan will re-trigger continuously. |
Bits 0, 1, 2, 3, 4, 5, 6 – CHNCMPEk Channel k Compare Enable
Bit 6 :CHNCMPE6 Enable digital comparator for processing ADC3 conversion results for internal IVREF 1.2V
Bit 5 :CHNCMPE5 Enable digital comparator for processing ADC3 conversion results for ADC3_AIN5
Bit 4 :CHNCMPE4 Enable digital comparator for processing ADC3 conversion results for ADC3_AIN4
Bit 3 :CHNCMPE3 Enable digital comparator for processing ADC3 conversion results for ADC3_AIN3
Bit 2 :CHNCMPE2 Enable digital comparator for processing ADC3 conversion results for ADC3_AIN2
Bit 1 :CHNCMPE1 Enable digital comparator for processing ADC3 conversion results for ADC3_AIN1
Bit 0 :CHNCMPE0 Enable digital comparator for processing ADC3 conversion results for ADC3_AIN0
- In addition to setting the CHNCMPENn bit in this register, the associated ADC3 Digital Comparator must be also properly configured in its Digital Comparator Control Register, CMPCTRL3 as well as EVCTRL3.CMPEO.
- These bits are ignored if CTRLB.SWCNVEN = 1 and CTRLB.ADCORSEL = 0 and are Enabled Protected (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error).
| Value | Description |
|---|---|
| 0 | ADC3 analog channel is not monitored by ADC3 internal digital comparator |
| 1 | ADC3 analog channel conversion result is monitored by ADC3 internal digital comparator |