42.7.20 ADC2 Channel Configuration Registers 4 (ADC)

Table 42-26. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: CONFIG[2].CHNCFG4
Offset: 0x70
Reset: 0x00000000
Property: PAC Write-Protected, Enable-Protected

Bit 3130292827262524 
     TRGSRC6[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 2322212019181716 
 TRGSRC5[3:0]TRGSRC4[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 TRGSRC3[3:0]TRGSRC2[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 TRGSRC1[3:0]TRGSRC0[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00011001 

Bits 0:3, 4:7, 8:11, 12:15, 16:19, 20:23, 24:27 – TRGSRCk Conversion Trigger Source for channel k

Bits 27-24: TRGSRC6 ADC2 Sample/Conversion Trigger Source for internal analog Temperature Sensor input

Note: Before attempting to measure Temperature sensor it must first be enabled with SUPC.VREFCTRL.TSEN = 1.

Bits 23-20: TRGSRC5 ADC2 Sample/Conversion Trigger Source for analog input channel ADC2_AIN5 (1)

Bits 19-16: TRGSRC4 ADC2 Sample/Conversion Trigger Source for analog input channel ADC2_AIN4 (1)

Bits 15-12: TRGSRC3 ADC2 Sample/Conversion Trigger Source for analog input channel ADC2_AIN3

Bits 11-8: TRGSRC2 ADC2 Sample/Conversion Trigger Source for analog input channel ADC2_AIN2

Bits 7-4: TRGSRC1 ADC2 Sample/Conversion Trigger Source for analog input channel ADC2_AIN1

Bits 3-0: TRGSRC0 ADC2 Sample/Conversion Trigger Source for analog input channel ADC2_AIN0

TRGSRCnDescription (Trigger events start ADC sample/conversion sequence)
0000No Trigger
0001

ADC2 Global Software Trigger.

(Requires CTRLB.GSWTRG =1, CTRLB.GSWTRG is self-clearing after trigger event.)

0010ADC2 Global Level Software Trigger (Requires CTRLB.LSWTRG=1)
0011(1)ADC2 SCANTRG - Scan Trigger. (Requires CHNCFG22.CSSy be configured accordingly)
0100ADC2 STRIG Synchronous Trigger
0101-1111ADC2 Trigger Event(s) from Event System (EVSYS)

If CHNCFG42.TRGSRCy = 0b101 thru 0b1111:

Event System (EVSYS)ADC2
CHANNELx.EVGENCHANNELn.PATH(2)USERm.CHANNELCHNCFG42.TRGSRCy
User Selected

ADC2 Trigger Event Source

= 0x2

Asynchronous path

980b0101
990b0110
1000b0111
1010b1000
1020b1001
1030b1010
1040b1011
1050b1100
1060b1101
1070b1110
1080b1111
Note:
  1. SCANTRG in turn requires programming of CORCTRL2.STRGSRC to select its trigger source. Also, the appropriate CHNCFG22.CSSy bit must be set to include channel “y” in the scan started by the STRIGn trigger.
  2. Requires EVCTRL2.STARTEI = 1 to enable any trigger event(s) from Event System (EVSYS).
  3. If using the Event System (EVSYS) trigger for ADC1, Asynchronous CHANNELn.PATH = 0x2 must be used to guarantee deterministic ADC sample/convert trigger timing.
  4. These bits are Enabled Protected (Writes are ignored when CTRLA.ENABLE = 1 returns a bus error).
  5. If CTRLB.SWCNVEN = 1 and CTRLB.ADCORSEL = 0x2, all of these register bits are ignored.