42.7.23 ADC3 Channel Configuration Registers 3 (ADC)

Note: All bits are Enabled Protected (Writes are ignored when CTRLA.ENABLE = 1 returns a bus error).

Table 42-29. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CONFIG[3].CHNCFG3
Offset:	0x8C
Reset:	0x00000000
Property:	PAC Write-Protected, Enable-Protected

Bits 16, 17, 18, 19, 20, 21, 22 – SIGNk Signed Data Output Format Enable for channel k

Bit 22: SIGN6 Signed Data Output Format Enable for ADC Module 3, analog internal 1.2v IVREF

Bit 21: SIGN5 Signed Data Output Format Enable for ADC Module 3, analog input ADC3_AIN5⁽¹⁾

Bit 20: SIGN4 Signed Data Output Format Enable for ADC Module 3, analog input ADC3_AIN4⁽¹⁾

Bit 19: SIGN3 Signed Data Output Format Enable for ADC Module 3, analog input ADC3_AIN3

Bit 18: SIGN2 Signed Data Output Format Enable for ADC Module 3, analog input ADC3_AIN2

Bit 17: SIGN1 Signed Data Output Format Enable for ADC Module 3, analog input ADC3_AIN1

Bit 16: SIGN0 Signed Data Output Format Enable for ADC Module 3, analog input ADC3_AIN0

Value	Description
0	Output format is unsigned
1	Output format is signed

Note: If SIGN mode desired for DIFF4 Differential mode then users must set SIGN4 = 1, SIGN5 = 0.

Value	Description
0	ADC3 inputs ADC3_AIN4 and ADC3_AIN5 are in single-ended input mode.
1	ADC3 inputs ADC3_AIN4(+) and ADC3_AIN5(-) are in differential input mode as differential pair.

Note: If SIGN mode desired for DIFF2 Differential mode then users must set SIGN2 = 1, SIGN3 = 0.

Value	Description
0	ADC3 inputs ADC3_AIN2 and ADC3_AIN3 are in single-ended input mode
1	ADC3 inputs ADC3_AIN2(+) and ADC3_AIN3(-) are in differential input mode as differential pair.

Note: If SIGN mode desired for DIFF0 Differential mode then users must set SIGN0 = 1, SIGN1 = 0.

Value	Description
0	ADC3 inputs ADC3_AIN0 and ADC3_AIN1 are in single-ended input mode
1	ADC3 inputs ADC3_AIN0(+) and ADC3_AIN1(-) are in differential input mode as differential pair.