42.7.7 ADC0 Channel Configuration Registers 2 (ADC)
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CONFIG[0].CHNCFG2 |
| Offset: | 0x28 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protected, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FRAC15 | FRAC14 | FRAC13 | FRAC12 | FRAC11 | FRAC10 | FRAC9 | FRAC8 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FRAC7 | FRAC6 | FRAC5 | FRAC4 | FRAC3 | FRAC2 | FRAC1 | FRAC0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CSS15 | CSS14 | CSS13 | CSS12 | CSS11 | CSS10 | CSS9 | CSS8 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CSS7 | CSS6 | CSS5 | CSS4 | CSS3 | CSS2 | CSS1 | CSS0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – FRACk Fractional Data Output Format Enable for Channel k
Bit 31: FRAC15 Fractional Data Output Format select for ADC Module 0, analog input ADC0_AIN15
Bit 30: FRAC14 Fractional Data Output Format select for ADC Module 0, analog input ADC0_AIN14
Bit 29: FRAC13 Fractional Data Output Format select for ADC Module 0, analog input ADC0_AIN13
Bit 28: FRAC12 Fractional Data Output Format select for ADC Module 0, analog input ADC0_AIN12
Bit 27: FRAC11 Fractional Data Output Format select for ADC Module 0, analog input ADC0_AIN11
Bit 26: FRAC10 Fractional Data Output Format select for ADC Module 0, analog input ADC0_AIN10
Bit 25: FRAC9 Fractional Data Output Format select for ADC Module 0, analog input ADC0_AIN9
Bit 24: FRAC8 Fractional Data Output Format select for ADC Module 0, analog input ADC0_AIN8
Bit 23: FRAC7 Fractional Data Output Format select for ADC Module 0, analog input ADC0_AIN7
Bit 22: FRAC6 Fractional Data Output Format select for ADC Module 0, analog input ADC0_AIN6
Bit 21: FRAC5 Fractional Data Output Format select for ADC Module 0, analog input ADC0_AIN5
Bit 20: FRAC4 Fractional Data Output Format select for ADC Module 0, analog input ADC0_AIN4
Bit 19: FRAC3 Fractional Data Output Format select for ADC Module 0, analog input ADC0_AIN3
Bit 18: FRAC2 Fractional Data Output Format select for ADC Module 0, analog input ADC0_AIN2
Bit 17: FRAC1 Fractional Data Output Format select for ADC Module 0, analog input ADC0_AIN1
Bit 16: FRAC0 Fractional Data Output Format select for ADC Module 0, analog input ADC0_AIN0
- These bits are ignored if CTRLB.SWCNVEN = 1 and CTRLB.ADCORSEL = 0x0
- These bits are Enabled Protected (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)
- Fractional format is very useful in MAC, (Multiply and Accumulate), operations since result overruns cannot happen since any given result is less than 1.
| Value | Description |
|---|---|
| 0 | ADC0 channel “AINn” result output format is unsigned integer |
| 1 | ADC0 channel “AINn” result output format is fractional |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – CSSk Channel Scan Select for Channel k
Bit 15: CSS15 Channel Scan Select for ADC Module 0, analog input ADC0_AIN15
Bit 14: CSS14 Channel Scan Select for ADC Module 0, analog input ADC0_AIN14
Bit 13: CSS13 Channel Scan Select for ADC Module 0, analog input ADC0_AIN13
Bit 12: CSS12 Channel Scan Select for ADC Module 0, analog input ADC0_AIN12
Bit 11: CSS11 Channel Scan Select for ADC Module 0, analog input ADC0_AIN11
Bit 10: CSS10 Channel Scan Select for ADC Module 0, analog input ADC0_AIN10
Bit 9: CSS9 Channel Scan Select for ADC Module 0, analog input ADC0_AIN9
Bit 8: CSS8 Channel Scan Select for ADC Module 0, analog input ADC0_AIN8
Bit 7: CSS7 Channel Scan Select for ADC Module 0, analog input ADC0_AIN7
Bit 6: CSS6 Channel Scan Select for ADC Module 0, analog input ADC0_AIN6
Bit 5: CSS5 Channel Scan Select for ADC Module 0, analog input ADC0_AIN5
Bit 4: CSS4 Channel Scan Select for ADC Module 0, analog input ADC0_AIN4
Bit 3: CSS3 Channel Scan Select for ADC Module 0, analog input ADC0_AIN3
Bit 2: CSS2 Channel Scan Select for ADC Module 0, analog input ADC0_AIN2
Bit 1: CSS1 Channel Scan Select for ADC Module 0, analog input ADC0_AIN1
Bit 0: CSS0 Channel Scan Select for ADC Module 0, analog input ADC0_AIN0
- Scan mode requires programming of CORCTRL0.SCANTRG and CORCTRL0.STRGSRC to select scan trigger source.
- ADC Scan sequence is always least to most significant analog input.
- These register bits are ignored if CTRLB.SWCNVEN = 1 and CTRLB.ADCORSEL= 0x0 and they are enabled Protected (Writes are ignored when CTRLA.ENABLE = 1 returns a bus error).
| Value | Description |
|---|---|
| 0 | ADC0 analog input channel “AINn” is not part of ADC scan list |
| 1 | Add ADC0 analog input channel “AINn” to scan list |