42.7.26 ADCn Digital Filter Control Register (ADC)
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | FLTCTRL[n] |
| Offset: | 0xC0 + n*0x04 [n=0..3] |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protected, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FLTCHNID[3:0] | FLTEN | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DATA16EN | FMODE | OVRSAM[2:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bits 13:10 – FLTCHNID[3:0] ADCn Channel ID To Be Filtered
Identifies which input channel, k , is to be filtered by the Digital Filter.
| FLTCTRL0 | FLTCHNID[3:0] = ADC0 External analog inputs AIN0 to AIN15 (2,3,4) |
| FLTCTRL1 | FLTCHNID[3:0] = ADC1 External analog inputs AIN0 to AIN5 and internal AIN6= VDDCORE |
| FLTCTRL2 | FLTCHNID[3:0] = ADC2 External analog inputs AIN0 to AIN5 and internal AIN6=Temperature Sensor |
| FLTCTRL3 | FLTCHNID[3:0] = ADC3 External analog inputs AIN0 to AIN5 and internal AIN6= IVREF 1.2v |
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
Bit 8 – FLTEN Digital Filter Enable
When set, this bit enables the Digital Filter associated with ADCn to filter the output data generated by the ADCn . The input channel to be filtered is determined by FLTCHNID.
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
Bit 4 – DATA16EN Data 16 Bits Enable
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
This bit is significant only if FMODE = 1 (Averaging Mode) and CHNCFG2n.FRACTk= 1 (Fractional Output Mode, where k = FLTCHNID[3:0] is the chosen input for filtering) as follows:
| Value | Description |
|---|---|
| 0 | Only the first 12 bits are significant, followed by 4 zeros. |
| 1 | All 16 bits of the filter output data are significant |
Bit 3 – FMODE ADC Filter Mode
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
| Value | Description |
|---|---|
| 0 | Filtering in Oversampling Mode (power-up default) |
| 1 | Filtering in Averaging Mode |
Bits 2:0 – OVRSAM[2:0] Oversampling Ratio
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
Determines the number of samples generated in the burst mode used for computing one single filter output value.
The OVRSAM encoding depends on the FMODE setting as follows:
If FMODE = 0 (Oversampling Mode) then OVRSAM is encoded as follows:
| Value | Descripton |
|---|---|
| 000 | 4 samples, shift sum 1-bit to right, output data is 13-bits |
| 001 | 16 samples, shift sum 2-bits to right, output data is 14-bits |
| 010 | 64 samples, shift sum 3-bits to right, output data is 15-bits |
| 011 | 256 samples, shift sum 4-bits to right, output data is 16-bits |
| 100 | 2 samples, shift sum 0-bits to right, output data is in 12.1 format |
| 101 | 8 samples, shift sum 1-bit to right, output data is in 13.1 format |
| 110 | 32 samples, shift sum 2-bits to right, output data is in 14.1 format |
| 111 | 128 samples, shift sum 3-bits to right, output data is in 15.1 format |
If FMODE=1 (Averaging Mode), then OVRSAM is encoded as follows:
| Value | Descripton |
|---|---|
| 000 | 2 samples to be averaged |
| 001 | 4 samples to be averaged |
| 010 | 8 samples to be averaged |
| 011 | 16 samples to be averaged |
| 100 | 32 samples to be averaged |
| 101 | 64 samples to be averaged |
| 110 | 128 samples to be averaged |
| 111 | 256 samples to be averaged |