42.7.10 ADC0 Channel Configuration Registers 5 (ADC)
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CONFIG[0].CHNCFG5 |
| Offset: | 0x34 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protected, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TRGSRC15[3:0] | TRGSRC14[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TRGSRC13[3:0] | TRGSRC12[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TRGSRC11[3:0] | TRGSRC10[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TRGSRC9[3:0] | TRGSRC8[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | |
Bits 0:3, 4:7, 8:11, 12:15, 16:19, 20:23, 24:27, 28:31 – TRGSRCk Conversion Trigger Source for channel k
Bits 28-31: TRGSRC15 ADC0 Sample/Conversion Trigger Source for analog input channel ADC0_AIN15
Bits 24-27: TRGSRC14 ADC0 Sample/Conversion Trigger Source for analog input channel ADC0_AIN14
Bits 20-23: TRGSRC13 ADC0 Sample/Conversion Trigger Source for analog input channel ADC0_AIN13
Bits 16-19: TRGSRC12 ADC0 Sample/Conversion Trigger Source for analog input channel ADC0_AIN12
Bits 15-12: TRGSRC11 ADC0 Sample/Conversion Trigger Source for analog input channel ADC0_AIN11
Bits 11-8: TRGSRC10 ADC0 Sample/Conversion Trigger Source for analog input channel ADC0_AIN10
Bits 7-4: TRGSRC9 ADC0 Sample/Conversion Trigger Source for analog input channel ADC0_AIN9
Bits 3-0: TRGSRC8 ADC0 Sample/Conversion Trigger Source for analog input channel ADC0_AIN8
| TRGSRCn | Description (Trigger events start ADC sample/conversion sequence) |
|---|---|
| 0000 | No Trigger |
| 0001 |
ADC0 Global Software Trigger. (Requires CTRLB.GSWTRG =1, CTRLB.GSWTRG is self-clearing after trigger event.) |
| 0010 | ADC0 Global Level Software Trigger (Requires CTRLB.LSWTRG=1) |
| 0011 | ADC0 SCANTRG - Scan Trigger. (Requires CHNCFG20.CSSy be configured accordingly) |
| 0100 | ADC0 STRIG Synchronous Trigger |
| 0101-1111 | ADC0 Trigger Event(s) from Event System (EVSYS) |
If CHNCFG5.TRGSRCy = 0b101 thru 0b1111:
| Event System (EVSYS) | ADC0 | ||
|---|---|---|---|
| CHANNELx.EVGEN | CHANNELn.PATH(2) | USERm.CHANNEL | CHNCFG5.TRGSRCy |
|
User Selected ADC0 Trigger Event Source |
= 0x2 Asynchronous path | 78 | 0b0101 |
| 79 | 0b0110 | ||
| 80 | 0b0111 | ||
| 81 | 0b1000 | ||
| 82 | 0b1001 | ||
| 83 | 0b1010 | ||
| 84 | 0b1011 | ||
| 85 | 0b1100 | ||
| 86 | 0b1101 | ||
| 87 | 0b1110 | ||
| 88 | 0b1111 | ||
- SCANTRG in turn requires programming of CORCTRL0.STRGSRC to select its trigger source. Also, the appropriate CHNCFG20.CSSy bit must be set to include channel “y” in the scan started by the STRIGn trigger.
- Requires EVCTRL0.STARTEI = 1 to enable any trigger event(s) from Event System (EVSYS).
- If using Event System (EVSYS) trigger for ADC, Asynchronous CHANNELn.PATH = 0x2 must be used to guarantee deterministic ADC sample/convert trigger timing.
- These bits are Enabled Protected (Writes are ignored when CTRLA.ENABLE = 1 returns a bus error).
- If CTRLB.SWCNVEN=1 and CTRLB.ADCORSEL=0x0, all of these register bits are ignored.