42.7.6 ADC0 Channel Configuration Registers 1 (ADC)
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CONFIG[0].CHNCFG1 |
| Offset: | 0x24 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protected, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| LVL15 | LVL14 | LVL13 | LVL12 | LVL11 | LVL10 | LVL9 | LVL8 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| LVL7 | LVL6 | LVL5 | LVL4 | LVL3 | LVL2 | LVL1 | LVL0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CHNCMPE15 | CHNCMPE14 | CHNCMPE13 | CHNCMPE12 | CHNCMPE11 | CHNCMPE10 | CHNCMPE9 | CHNCMPE8 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHNCMPE7 | CHNCMPE6 | CHNCMPE5 | CHNCMPE4 | CHNCMPE3 | CHNCMPE2 | CHNCMPE1 | CHNCMPE0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – LVLk Trigger Level for Input k
Bit 31 :LVL15 Scan Level Trigger mode select for ADC Module 0, analog input ADC0_AIN15
Bit 30 :LVL14 Scan Level Trigger mode select for ADC Module 0, analog input ADC0_AIN14
Bit 29 :LVL13 Scan Level Trigger mode select for ADC Module 0, analog input ADC0_AIN13
Bit 28 :LVL12 Scan Level Trigger mode select for ADC Module 0, analog input ADC0_AIN12
Bit 27 :LVL11 Scan Level Trigger mode select for ADC Module 0, analog input ADC0_AIN11
Bit 26 :LVL10 Scan Level Trigger mode select for ADC Module 0, analog input ADC0_AIN10
Bit 25 :LVL9 Scan Level Trigger mode select for ADC Module 0, analog input ADC0_AIN9
Bit 24 :LVL8 Scan Level Trigger mode select for ADC Module 0, analog input ADC0_AIN8
Bit 23 :LVL7 Scan Level Trigger mode select for ADC Module 0, analog input ADC0_AIN7
Bit 22 :LVL6 Scan Level Trigger mode select for ADC Module 0, analog input ADC0_AIN6
Bit 21 :LVL5 Scan Level Trigger mode select for ADC Module 0, analog input ADC0_AIN5
Bit 20 :LVL4 Scan Level Trigger mode select for ADC Module 0, analog input ADC0_AIN4
Bit 19 :LVL3 Scan Level Trigger mode select for ADC Module 0, analog input ADC0_AIN3
Bit 18 :LVL2 Scan Level Trigger mode select for ADC Module 0, analog input ADC0_AIN2
Bit 17 :LVL1 Scan Level Trigger mode select for ADC Module 0, analog input ADC0_AIN1
Bit 16 :LVL0 Scan Level Trigger mode select for ADC Module 0, analog input ADC0_AIN0
- These bits are ignored if CTRLB.SWCNVEN = 1 and CTRLB.ADCORSEL= 0.
- These bits are Enabled Protected (Writes are ignored when CTRLA.ENABLE = 1 returns a bus error).
| Value | Description |
|---|---|
| 0 | Rising edge scan trigger mode select. A rising edge trigger event will initiate a single but complete scan of all included scan channels defined in CHNCFG21.CSSy (Default). |
| 1 | Level scan trigger mode select. As long as the trigger event stays a logic high when The corresponding CHNCFG40/ CHNCFG50 TRGSRCx = 0b0011, (SCANTRG - Scan Trigger Select), the entire scan will re-trigger continuously. |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – CHNCMPEk Channel k Compare Enable
Bit 15 :CHNCMPE15 Enable digital comparator for processing ADC0 conversion results for ADC0_AIN15
Bit 14 :CHNCMPE14 Enable digital comparator for processing ADC0 conversion results for ADC0_AIN14
Bit 13 :CHNCMPE13 Enable digital comparator for processing ADC0 conversion results for ADC0_AIN13
Bit 12 :CHNCMPE12 Enable digital comparator for processing ADC0 conversion results for ADC0_AIN12
Bit 11 :CHNCMPE11 Enable digital comparator for processing ADC0 conversion results for ADC0_AIN11
Bit 10 :CHNCMPE10 Enable digital comparator for processing ADC0 conversion results for ADC0_AIN10
Bit 9 :CHNCMPE9 Enable digital comparator for processing ADC0 conversion results for ADC0_AIN9
Bit 8 :CHNCMPE8 Enable digital comparator for processing ADC0 conversion results for ADC0_AIN8
Bit 7 :CHNCMPE7 Enable digital comparator for processing ADC0 conversion results for ADC0_AIN7
Bit 6 :CHNCMPE6 Enable digital comparator for processing ADC0 conversion results for ADC0_AIN6
Bit 5 :CHNCMPE5 Enable digital comparator for processing ADC0 conversion results for ADC0_AIN5
Bit 4 :CHNCMPE4 Enable digital comparator for processing ADC0 conversion results for ADC0_AIN4
Bit 3 :CHNCMPE3 Enable digital comparator for processing ADC0 conversion results for ADC0_AIN3
Bit 2 :CHNCMPE2 Enable digital comparator for processing ADC0 conversion results for ADC0_AIN2
Bit 1 :CHNCMPE1 Enable digital comparator for processing ADC0 conversion results for ADC0_AIN1
Bit 0 :CHNCMPE0 Enable digital comparator for processing ADC0 conversion results for ADC0_AIN0
- In addition to setting the CHNCMPENn bit in this register, the associated ADC0 Digital Comparator must be also properly configured in its Digital Comparator Control Register, CMPCTRL0 as well as EVCTRL0.CMPEO.
- These bits are ignored if CTRLB.SWCNVEN = 1 and CTRLB.ADCORSEL = 0 and are Enabled Protected (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)
| Value | Description |
|---|---|
| 0 | ADC0 analog channel is not monitored by ADC0 internal digital comparator |
| 1 | ADC0 analog channel conversion result is monitored by ADC0 internal digital comparator |