42.7.36 ADCn Interrupt Enable Set Register (ADC)

Note: Writing a zero to any of these bits has no effect, but writing a one to these bits will SET the ENABLE bit.

A read of this register provides the current status of interrupts, i.e., whether each interrupt is enabled (bit=1) or disabled (bit=0).

Table 42-42. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: INTENSET[n]
Offset: 0x0124 + n*0x10 [n=0..3]
Reset: 0x00000000
Property: PAC Write-Protected, Enable-Protected

Bit 3130292827262524 
 CHRDY[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 CHRDY[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
     EOSRDYCHNERRCFLTRDYCHRDYC 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 SOVFL  CMPHIT     
Access R/WR/W 
Reset 00 

Bits 31:16 – CHRDY[15:0] ADCn Channel Ready Interrupt Enable for Input Channel k of Core n

Writing a 1 to bit k will enable the data ready flag for Core n channel k as an interrupt request.

CHRDY[ k ] is defined only for k = 0,1,2,…,(Sn-1).

Note:
  1. This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)

Bit 11 – EOSRDY ADCn Module End-Of-Scan Interrupt Enable

Writing a 1 to this bit will disable the flag bit EOSRDY as an interrupt request.

Note:
  1. This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)

Bit 10 – CHNERRC ADCn Module Channel Overwritten Error Flag Interrupt Enable

Writing a 1 to this bit will enable the flag bit CHNERRC as an interrupt request.

Note:
  1. This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)

Bit 9 – FLTRDY ADCn Digital Filter Ready Flag Enable

Writing a 1 to this bit will enable the filter ready flag for Filter as an interrupt request.

Note:
  1. This bit is Enabled Protected: (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)

Bit 8 – CHRDYC ADCn Module Current Channel Ready Enable

Writing a 1 to this bit will enable the flag bit CHRDYC as an interrupt request.

Note:
  1. This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)

Bit 7 – SOVFL ADCn Clock Synchronizer Overflow Enable

Writing a 1 to this bit will enable the flag SOVFL as an interrupt request.

Note:
  1. This bit is Enabled Protected: (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)

Bit 4 – CMPHIT ADCn Digital Comparator Hit Enable

Writing a 1 to this bit will enable the comparator hit flag for Comparator n as an interrupt request.

Note:
  1. This bit is Enabled Protected: (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)