42.7.19 ADC2 Channel Configuration Registers 3 (ADC)
Note: All bits are Enabled Protected
(Writes are ignored when CTRLA.ENABLE = 1 returns a bus error).
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CONFIG[2].CHNCFG3 |
| Offset: | 0x6C |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protected, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SIGNn | SIGNn | SIGNn | SIGNn | SIGNn | SIGNn | SIGNn | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIFF4 | DIFF2 | DIFF0 | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bits 16, 17, 18, 19, 20, 21, 22 – SIGNn Signed Data Output Format Enable for channel n
Note: Before attempting to measure Temperature sensor it must first be enabled with
SUPC.VREFCTRL.TSEN = 1.
Bit 22: SIGN6 Signed Data Output Format Enable for ADC Module 2, analog
internal Temperature Sensor
Note: Before attempting to measure Temperature
sensor it must first be enabled with SUPC.VREFCTRL.TSEN = 1 and wait 20us if
previously SUPC.VREFCTRL.TSEN = 0 for warm up stabilization time. Then
Minimum ADC sample time required SAMC=0x300.
Bit 21: SIGN5 Signed Data Output Format Enable for ADC Module 2, analog input ADC2_AIN5 (1)
Bit 20: SIGN4 Signed Data Output Format Enable for ADC Module 2, analog input ADC2_AIN4 (1)
Bit 19: SIGN3 Signed Data Output Format Enable for ADC Module 2, analog input ADC2_AIN3
Bit 18: SIGN2 Signed Data Output Format Enable for ADC Module 2, analog input ADC2_AIN2
Bit 17: SIGN1 Signed Data Output Format Enable for ADC Module 2, analog input ADC2_AIN1
Bit 16: SIGN0 Signed Data Output Format Enable for ADC Module 2, analog input ADC2_AIN0
| Value | Description |
|---|---|
| 0 | Output format is unsigned |
| 1 | Output format is signed |
Bit 4 – DIFF4 Differential Mode Enable for ADC2, ADC2_AIN4(+), and ADC2_AIN5(-) analog input channels
Note: If SIGN mode desired for DIFF4
Differential mode then users must set SIGN4 = 1, SIGN5 = 0.
| Value | Description |
|---|---|
| 0 | ADC2 inputs ADC2_AIN4 and ADC2_AIN5 are in single ended input mode. |
| 1 | ADC2 inputs ADC2_AIN4(+) and ADC2_AIN5(-) are in differential input mode as differential pair. |
Bit 2 – DIFF2 Differential Mode Enable for ADC2, ADC2_AIN2(+), and ADC2_AIN3(-) analog input channels
Note: If SIGN mode desired for DIFF2
Differential mode then user must set SIGN2 = 1, SIGN3 = 0.
| Value | Description |
|---|---|
| 0 | ADC2 inputs ADC2_AIN2 and ADC2_AIN3 are in single-ended input mode |
| 1 | ADC2 inputs ADC2_AIN2(+) and ADC2_AIN3(-) are in differential input mode as differential pair. |
Bit 0 – DIFF0 Differential Mode Enable for ADC2, ADC2_AIN0(+), and ADC2_AIN1(-) analog input channels
Note: If SIGN mode desired for DIFF0 Differential mode then user must set SIGN0=1,
SIGN1=0.
| Value | Description |
|---|---|
| 0 | ADC2 inputs ADC2_AIN0 and ADC2_AIN1 are in single-ended input mode |
| 1 | ADC2 inputs ADC2_AIN0(+) and ADC2_AIN1(-) are in differential input mode as differential pair. |