42.7.27 ADC COR Channel Ready DATA ID Register (ADC)

Table 42-33. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: CORCHDATAID
Offset: 0xD0
Reset: 0x00000000
Property: PAC Write-Protected, Enable-Protected

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
   CORDYID[1:0]CHRDYID[3:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bits 5:4 – CORDYID[1:0] ADC Channel Read ID

ADCn where n= Index:

Set value to ADCn index for which status register CHNRDYDAT is going to display the current values of configuration bits and the last converted output data or written by the user to display the channel.

ValueDescription
11ADC3
10ADC2
01ADC1
00ADC0

Bits 3:0 – CHRDYID[3:0] ADC Channel Read ID

Input Channel Index k:

For ADCn , set value to input channel index, k,0 ≤ k ≤ (Sn-1) for status register CHNRDYDAT to display the current values of configuration bits and the last converted output data or written by the user to display the channel.

Note:
  1. ADC0 supports external analog inputs AIN0 - AIN15,

    ADC1 supports external analog inputs AIN0 - AIN5 and internal AIN6 VDDCORE.

    ADC2 supports external analog inputs AIN0 - AIN5 and internal AIN6 Temperature Sensor .

    ADC3 supports external analog inputs AIN0 - AIN5 and internal AIN6 IVREF 1.2V .

  2. Selecting unimplemented input channels on a given ADCn will return a bus error with the data (32’h00000000).
ValueDescription
1111analog input channel 15 (1)
1110analog input channel 14(1)
......
0010analog input channel 2
0001analog channel 1
0000analog channel 0