42.7.14 ADC1 Channel Configuration Registers 2 (ADC)
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CONFIG[1].CHNCFG2 |
| Offset: | 0x48 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protected, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FRAC6 | FRAC5 | FRAC4 | FRAC3 | FRAC2 | FRAC1 | FRAC0 | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CSS6 | CSS5 | CSS4 | CSS3 | CSS2 | CSS1 | CSS0 | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 16, 17, 18, 19, 20, 21, 22 – FRACk Fractional Data Output Format Enable for Channel k
Bit 22: FRAC6 Fractional Data Output Format select for ADC Module 1, internal analog input VDDCORE
Bit 21: FRAC5 Fractional Data Output Format select for ADC Module 1, analog input ADC1_AIN5
Bit 20: FRAC4 Fractional Data Output Format select for ADC Module 1, analog input ADC1_AIN4
Bit 19: FRAC3 Fractional Data Output Format select for ADC Module 1, analog input ADC1_AIN3
Bit 18: FRAC2 Fractional Data Output Format select for ADC Module 1, analog input ADC1_AIN2
Bit 17: FRAC1 Fractional Data Output Format select for ADC Module 1, analog input ADC1_AIN1
Bit 16: FRAC0 Fractional Data Output Format select for ADC Module 1, analog input ADC1_AIN0
- These bits are ignored if CTRLB.SWCNVEN = 1 and CTRLB.ADCORSEL = 0x1.
- These bits are Enabled Protected (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)
- Fractional format is very useful in MAC, (Multiply and Accumulate), operations since result overruns can’t happen since any given result is less than 1.
| Value | Description |
|---|---|
| 0 | ADC1 channel “AINn” result output format is unsigned integer |
| 1 | ADC1 channel “AINn” result output format is fractional |
Bits 0, 1, 2, 3, 4, 5, 6 – CSSk Channel Scan Select for Channel k
Bit 6: CSS6 Channel Scan Select for ADC Module 1, internal analog input VDDCORE
Bit 5: CSS5 Channel Scan Select for ADC Module 1, analog input ADC1_AIN
Bit 4: CSS4 Channel Scan Select for ADC Module 1, analog input ADC1_AIN4
Bit 3: CSS3 Channel Scan Select for ADC Module 1, analog input ADC1_AIN3
Bit 2: CSS2 Channel Scan Select for ADC Module 1, analog input ADC1_AIN2
Bit 1: CSS1 Channel Scan Select for ADC Module 1, analog input ADC1_AIN1
Bit 0: CSS0 Channel Scan Select for ADC Module 1, analog input ADC1_AIN0
- Scan mode requires programming of CORCTRL1.SCANTRG and CORCTRL1.STRGSRC to select scan trigger source.
- ADC Scan sequence is always least to most significant analog input.
- These register bits are ignored if CTRLB.SWCNVEN = 1 and CTRLB.ADCORSEL = 0x0 and they are enabled Protected (Writes are ignored when CTRLA.ENABLE = 1 returns a bus error).
| Value | Description |
|---|---|
| 0 | ADC1 analog input channel “AINn” is not part of ADC scan list |
| 1 | Add ADC1 analog input channel “AINn” to scan list |