42.7.14 ADC1 Channel Configuration Registers 2 (ADC)

Table 42-20. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: CONFIG[1].CHNCFG2
Offset: 0x48
Reset: 0x00000000
Property: PAC Write-Protected, Enable-Protected

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
  FRAC6FRAC5FRAC4FRAC3FRAC2FRAC1FRAC0 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
  CSS6CSS5CSS4CSS3CSS2CSS1CSS0 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bits 16, 17, 18, 19, 20, 21, 22 – FRACk Fractional Data Output Format Enable for Channel k

Bit 22: FRAC6 Fractional Data Output Format select for ADC Module 1, internal analog input VDDCORE

Bit 21: FRAC5 Fractional Data Output Format select for ADC Module 1, analog input ADC1_AIN5

Bit 20: FRAC4 Fractional Data Output Format select for ADC Module 1, analog input ADC1_AIN4

Bit 19: FRAC3 Fractional Data Output Format select for ADC Module 1, analog input ADC1_AIN3

Bit 18: FRAC2 Fractional Data Output Format select for ADC Module 1, analog input ADC1_AIN2

Bit 17: FRAC1 Fractional Data Output Format select for ADC Module 1, analog input ADC1_AIN1

Bit 16: FRAC0 Fractional Data Output Format select for ADC Module 1, analog input ADC1_AIN0

Note:
  1. These bits are ignored if CTRLB.SWCNVEN = 1 and CTRLB.ADCORSEL = 0x1.
  2. These bits are Enabled Protected (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)
  3. Fractional format is very useful in MAC, (Multiply and Accumulate), operations since result overruns can’t happen since any given result is less than 1.
ValueDescription
0ADC1 channel “AINn” result output format is unsigned integer
1ADC1 channel “AINn” result output format is fractional

Bits 0, 1, 2, 3, 4, 5, 6 – CSSk Channel Scan Select for Channel k

Bit 6: CSS6 Channel Scan Select for ADC Module 1, internal analog input VDDCORE

Bit 5: CSS5 Channel Scan Select for ADC Module 1, analog input ADC1_AIN

Bit 4: CSS4 Channel Scan Select for ADC Module 1, analog input ADC1_AIN4

Bit 3: CSS3 Channel Scan Select for ADC Module 1, analog input ADC1_AIN3

Bit 2: CSS2 Channel Scan Select for ADC Module 1, analog input ADC1_AIN2

Bit 1: CSS1 Channel Scan Select for ADC Module 1, analog input ADC1_AIN1

Bit 0: CSS0 Channel Scan Select for ADC Module 1, analog input ADC1_AIN0

Note:
  1. Scan mode requires programming of CORCTRL1.SCANTRG and CORCTRL1.STRGSRC to select scan trigger source.
  2. ADC Scan sequence is always least to most significant analog input.
  3. These register bits are ignored if CTRLB.SWCNVEN = 1 and CTRLB.ADCORSEL = 0x0 and they are enabled Protected (Writes are ignored when CTRLA.ENABLE = 1 returns a bus error).
ValueDescription
0ADC1 analog input channel “AINn” is not part of ADC scan list
1Add ADC1 analog input channel “AINn” to scan list