42.7.35 ADCn Interrupt Enable Clear (ADC)
A read of this register provides the current status of interrupts, i.e., whether each interrupt is enabled (bit=1) or disabled (bit=0).
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTENCLR[n] |
| Offset: | 0x0120 + n*0x10 [n=0..3] |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protected, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CHRDY[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CHRDY[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EOSRDY | CHNERRC | FLTRDY | CHRDYC | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SOVFL | CMPHIT | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bits 31:16 – CHRDY[15:0] ADCn Channel Ready Interrupt Disable for Input Channel k of Core n
Writing a 1 to bit will k disable the data ready flag for Core n channel k as an interrupt request.
CHRDY[ k ] is defined only for k = 0,1,2,…,(Sn-1).
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)
Bit 11 – EOSRDY ADCn Module End-Of-Scan Interrupt Disable
Writing a 1 to this bit will disable the flag bit EOSRDY as an interrupt request.
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)
Bit 10 – CHNERRC ADCn Module Channel Overwritten Error Flag Interrupt Disable
Writing a 1 to this bit will disable the flag bit CHNERRCas an interrupt request.
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)
Bit 9 – FLTRDY ADCn Digital Filter Ready Flag Disable
Writing a 1 to this bit will disable the filter ready flag for Filter as an interrupt request.
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)
Bit 8 – CHRDYC ADCn Module Current Channel ready Disable
Writing a 1 to this bit will disable the flag bit CHRDYC as an interrupt request.
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)
Bit 7 – SOVFL ADCn Clock Synchronizer Overflow Disable
Writing a 1 to this bit will disable the flag SOVFL as an interrupt request.
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)
Bit 4 – CMPHIT ADCn Digital Comparator Hit Disable
Writing a 1 to this bit will disable the comparator hit flag for Comparator n as an interrupt request.
- This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error.)