42.7.16 ADC1 Channel Configuration Registers 4 (ADC)
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CONFIG[1].CHNCFG4 |
| Offset: | 0x50 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protected, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TRGSRC6[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TRGSRC5[3:0] | TRGSRC4[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TRGSRC3[3:0] | TRGSRC2[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TRGSRC1[3:0] | TRGSRC0[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | |
Bits 0:3, 4:7, 8:11, 12:15, 16:19, 20:23, 24:27 – TRGSRCk Conversion Trigger Source for channel k
Bits 27-24: TRGSRC6 ADC1 Sample/Conversion Trigger Source for internal analog input channel from VDDCORE
Bits 23-20: TRGSRC5 ADC1 Sample/Conversion Trigger Source for analog input channel ADC1_AIN5 (1)
Bits 19-16: TRGSRC4 ADC1 Sample/Conversion Trigger Source for analog input channel ADC1_AIN4 (1)
Bits 15-12: TRGSRC3 ADC1 Sample/Conversion Trigger Source for analog input channel ADC1_AIN3
Bits 11-8: TRGSRC2 ADC1 Sample/Conversion Trigger Source for analog input channel ADC1_AIN2
Bits 7-4: TRGSRC1 ADC1 Sample/Conversion Trigger Source for analog input channel ADC1_AIN1
Bits 3-0: TRGSRC0 ADC1 Sample/Conversion Trigger Source for analog input channel ADC1_AIN0
| TRGSRCn | Description (Trigger events start ADC sample/conversion sequence) |
|---|---|
| 0000 | No Trigger |
| 0001 |
ADC1 Global Software Trigger. (Requires CTRLB.GSWTRG =1, CTRLB.GSWTRG is self-clearing after trigger event.) |
| 0010 | ADC1 Global Level Software Trigger (Requires CTRLB.LSWTRG=1) |
| 0011(1) | ADC1 SCANTRG - Scan Trigger. (Requires CHNCFG21.CSSy be configured accordingly) |
| 0100 | ADC1 STRIG Synchronous Trigger |
| 0101-1111 | ADC1 Trigger Event(s) from Event System (EVSYS) |
If CHNCFG41.TRGSRCy = 0b101 thru 0b1111:
| Event System (EVSYS) | ADC1 | ||
|---|---|---|---|
| CHANNELx.EVGEN | CHANNELn.PATH(2) | USERm.CHANNEL | CHNCFG41.TRGSRCy |
| User
Selected ADC1 Trigger Event Source | =
0x2 Asynchronous path | 98 | 0b0101 |
| 99 | 0b0110 | ||
| 100 | 0b0111 | ||
| 101 | 0b1000 | ||
| 102 | 0b1001 | ||
| 103 | 0b1010 | ||
| 104 | 0b1011 | ||
| 105 | 0b1100 | ||
| 106 | 0b1101 | ||
| 107 | 0b1110 | ||
| 108 | 0b1111 | ||
- SCANTRG in turn requires programming of CORCTRL1.STRGSRC to select its trigger source. Also, the appropriate CHNCFG21.CSSy bit must be set to include channel “y” in the scan started by the STRIGn trigger.
- Requires EVCTRL1.STARTEI = 1 to enable any trigger event(s) from Event System (EVSYS).
- If using the Event System (EVSYS) trigger for ADC1, Asynchronous CHANNELn.PATH = 0x2 must be used to guarantee deterministic ADC sample/convert trigger timing.
- These bits are Enabled Protected (Writes are ignored when CTRLA.ENABLE = 1 returns a bus error. )
- If CTRLB.SWCNVEN=1 and CTRLB.ADCORSEL=0x1, all of these register bits are ignored.