42.7.3 Control Register C (ADC)
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLC |
| Offset: | 0x8 |
| Reset: | 0x00000000 |
| Property: | Write-Protected, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| COREINTERLEAVED[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CNT[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CNT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 30:28 – COREINTERLEAVED[2:0]
| Number of
Interleaved ADCs Used | Interleaved ADC Modules | CTRLC. CORINTERLEAVED | 12-bit Msps (Max) [Min. Trigger rate] | 10-bit Msps (Max) [Min. Trigger rate] | 8-bit Msps (Max) [Min. Trigger rate] | 6-bit Msps (Max) [Min. Trigger rate] |
|---|---|---|---|---|---|---|
| 2 | 1,2 | =0b001 | 1 / (8 * TAD) [8 TAD] | 1/ (7 * TAD) [7 TAD] | 1/ (6 * TAD) [6 TAD] | 1 / (4.5 * TAD) [4.5 TAD] |
| 0,1 | =0b100 | 1 / (10 * TAD) [10 TAD] | 1/ (8.5 * TAD) [8.5 TAD] | 1/ (7,5 * TAD) [7.5 TAD] | 1 / (6.5 * TAD) [6.5 TAD] | |
| 3 | 1,2,3 | =0b010 | 1 / (5.5 * TAD) [5.5 TAD] | 1/ (5 * TAD) [5 TAD] | 1 / (4 *TAD) [4 TAD] | 1 / (3 * TAD) [3 TAD] |
| 0,1,2 | =0b101 | 1 / (6.5 * TAD) [6.5 TAD] | 1 / (6 * TAD) [6 TAD] | 1 / (5 * TAD) [5 TAD] | 1 / (4.5 * TAD) [4.5 TAD] | |
| 4 | 0,1,2,3 | =0b011 | 1 / (5 * TAD) [5 TAD] | 1 / (4.5 * TAD) [4.5 TAD] | 1 / (4 *TAD) [4 TAD] | 1 / (3.5 * TAD) [3.5 TAD] |
Minimum CORCTRLn.SAMC sample time values for 12/10/8/6-bit resolution
- ADC0: CORCTRL0.SAMC = 4 (i.e., = 6 TAD sample time)
- ADC1: CORCTRL1.SAMC = 1 (i.e., = 3 TAD sample time)
- ADC2: CORCTRL2.SAMC = 1 (i.e., = 3 TAD sample time)
- ADC3: CORCTRL3.SAMC = 1 (i.e., = 3 TAD sample time)
- Conversion Time = (#bits resolution + 1)
- The table above assumes event trigger source GCLK is 2x GCLK_ADC. This is what allows 0.5 TAD increments. If not, and trigger source GCLK is equal to GCLK_ADC, then maximum throughput rate and minimum trigger rate must be rounded up to next whole integer TAD value.
- TAD is the ADC_CLOCK
period time in nano seconds, refer to the ADC Electrical
Specifications.
ADCn TAD = GLK_ADC / [(CTRLB.CTLCKDIV +1) * (CORCTRLn.ADCDIV * 2)]
- Assumes EVSYS trigger peripheral clock = (2 / TAD) = (2 * GCLK_ADC).
- Must use the same analog input AINx on ADCn modules being interleaved.
- These bits are Enabled Protected, and rites are ignored when CTRLA.ENABLE = 1 and will return a bus error.
- ADC0, due to the higher number of analog inputs it services have a higher minimum CORCTRLn.SAMC sample time that the user must consider since the slowest ADC affects the maximum combination of ADC interleaved through put rate. ADC 1, 2, and 3 have an identical CORCTRLn.SAMC minimum sample time.
| Value | Description |
|---|---|
| 000 | Interleaving off |
| 100 | Interleaving cores 0,1 |
| 001 | Interleaving cores 1,2 |
| 101 | Interleaving cores 0,1,2 |
| 010 | Interleaving cores 1,2,3 |
| 011 | Interleaving cores 0,1,2,3 |
| 100-111 | Reserved |
Bits 15:0 – CNT[15:0] This bit-field selects an alternate trigger source delay counter
Free-running counter based on CTL_CLK times out when it reaches this value. At time out, the STRIG synchronous trigger will fire.
- This register is not valid unless either [CORCTRLn.STRGSRC = 0x4 plus CHNCFG4/5n.TRGSRCx = 0x3 plus CHNCFG2n.CSSx = 1] or [CHNCFG4n.TRGSRCx = 0x4 plus CTRLB.SWCNVEN = 0] for Synchronous Trigger from CTRLC.CNT.
- CTL_CLK = GCLK_ADC / (CTRLD.CTLCKDIV+1).
- This bit is Enabled Protected (writes are ignored when CTRLA.ENABLE = 1 and return a bus error).