42.7.4 Control Register D (ADC)
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLD |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Property: | Write-Protected, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| VREFSEL[2:0] | WKUPCLKCNT[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ANLEN3 | ANLEN2 | ANLEN1 | ANLEN0 | CHNEN3 | CHNEN2 | CHNEN1 | CHNEN0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CTLCKDIV[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bits 30:28 – VREFSEL[2:0] VREF Input Selection
| VREFSEL[2:0] | ADREF+ | ADREF- |
|---|---|---|
000 | AVDD | AVSS |
001 | External VREFH | AVSS |
010-111 | Reserved | Reserved |
Note:
- This bit is Enabled Protected. Writes are ignored when CTRLA.ENABLE = 1 and return a bus error.
Bits 27:24 – WKUPCLKCNT[3:0] Wake-Up TAD Clock Count bits
These bits represent the number of ADC TAD clocks required to warm-up the ADC module before it can perform conversion. Although the clocks are specific to each ADC, the WKUPCLKCNT bit is common to all ADC modules.
1111 = 215 = 32,768 TAD clocks
* * *
* * *
0110 = 26 = 64 TAD clocks
0101 = 25 = 32 TAD clocks
0100 = 24 = 16 TAD clocks
0011 = 24 = 16 TAD clocks
0010 = 24 = 16 TAD clocks
0001 = 24 = 16 TAD clocks
0000 = 24 = 16 TAD clocks
Note:
- Minimum required ADCx warm-up time (i.e., WKUPCLKCNT) is 50 μs. (i.e., TAD * WKUPCLKCNT).
- TAD = [1 / ((GCLK_ADCx
Freq / (CTRLD.CTLCKDIV+1)) / (2 * CORCTRLn.ADCDIV)) ] or
(GCLK_ADCx Period * (CTRLD.CTLCKDIV+1)) * (2 * ADCDIV).
- These bits are Enabled Protected. Writes are ignored when CTRLA.ENABLE = 1 and return a bus error.
- After enabling the Analog and Bias Circuitry for the ADC Module x, CTRLD.ANLENx = 1, the user must poll the CTLINTFLAG.CRRDYx flag and wait for it to be set before allowing any ADC trigger events or ADC sample/conversions to begin. Failure to do so will yield inaccurate results for up to 50 us.
- After enabling the CTRLD.CHNENn ADC module digital logic it only requires one TAD clock before the digital logic is ready.
Bits 20, 21, 22, 23 – ANLENx Analog and Bias Circuitry Enable for the ADC module x
Note:
- The CALCTRL0 register must be initialized by the user software to the factory-provided values in the Calibration Configuration Register FCCFG65 before setting ANLENx = 1. This applies to every ADC module that will be used by
- CTRLA.ANAEN = 1 must be set prior to setting ANLENx = 1.
- This bit is Enabled Protected. Writes are ignored when CTRLA.ENABLE = 1 and return a bus error.
| Value | Description |
|---|---|
| 0 | ADC3 Analog and bias circuitry powered down and clocks suspended. Analog logic power saving mode. |
| 1 | Analog and bias circuitry enabled. Once the analog and bias circuit is enabled CTRLA.ANLEN = 1 and ANLENx, the ADC module needs a warm-up time, as defined by the WKUPCLKCNT<3:0> bits. |
Bits 16, 17, 18, 19 – CHNENn ADC Module n Digital Enable
Note:
- This bit is Enabled Protected. Writes are ignored when CTRLA.ENABLE = 1 and return a bus error.
- ANLENn qualifies CHNENn: If ANLENn = 0, then digital logic is also disabled.
| Value | Description |
|---|---|
| 0 | ADCn digital logic disabled. No trigger, sample or conversion events will be processed. (power-saving mode with fast 2 TAD clock wakeup provided ANLENn = 1). |
| 1 | ADCn digital logic enabled (required for active operation). |
Bits 13:8 – CTLCKDIV[5:0] A/D Clock Source to Control Clock Divider
The CTLCKDIV bit field divides the GCLK_ADC input clock into the ADC Module control clock CTL_CLK scaled by CTRLD.CTLCKDIV with period TQ.
Note: This bit is Enabled Protected. Writes are ignored when CTRLA.ENABLE = 1 and
returns a bus error.
| Value | Description |
|---|---|
| 111111 | TGCLK_ADCx·(CTLCKDIV[5:0]+1) = 64·TGCLK_ADCx = TQ |
| 111110 | TGCLK_ADCx·(CTLCKDIV[5:0]+1) = 63·TGCLK_ADCx = TQ |
| ... | ... |
| 000100 | TGCLK_ADCx·(CTLCKDIV[5:0]+1) = 5·TGCLK_ADCx = TQ |
| 000011 | TGCLK_ADCx·(CTLCKDIV[5:0]+1) = 4·TGCLK_ADCx = TQ |
| 000010 | TGCLK_ADCx·(CTLCKDIV[5:0]+1) = 3·TGCLK_ADCx = TQ |
| 000001 | TGCLK_ADCx·(CTLCKDIV[5:0]+1) = 2·TGCLK_ADCx = TQ |
| 000000 | TGCLK_ADCx·(CTLCKDIV[5:0]+1) = 1·TGCLK_ADCx = TQ |