42.7.31 ADC Core Synchronization Register (ADC)
Note: The following GCLK-clocked
registers are “Enable Write Protected”:
- CTRLC
- CTRLD
- CORCTRLn
- CHNCFG1n
- CHNCFG2n
- CHNCFG3n
- CHNCFG4n
- CHNCFG5n
- CALTRLn
- FLTCTRLn
Therefore, they do not require a SyncBusy bit. These registers are write-disabled when the CTRLA.ENABLE bit is set to enable the ADC. They can only be changed when the ADC is disabled (CTRLA.ENABLE = 0). The user must completely configure the ADC and then enable the ADC by setting CTRLA.ENABLE = 1.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | SYNCBUSY |
| Offset: | 0xE8 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CTRLB | ENABLE | SWRST | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
Bit 2 – CTRLB Synchronization Busy bit
For the GCLK-based register CTRLB:
When Hardware sets this bit, no writes are permitted to the CTRLB register.
Bit 1 – ENABLE ENABLE Synchronization Busy bit
For GCLK-based register bit CTRLA.ENABLE:
When Hardware sets this bit, no writes are permitted to the CTRLA.ENABLE register.
Bit 0 – SWRST Software Reset Busy bit
Note:
- Typically, when the SWRST is written, the bit is auto-cleared the next APB clock cycle after. However, the SYNCBUSY.SWRST bit is set and stays set until the reset in the GCLK domain is completed. So, the user must poll the SYNCBUSY register to know when the operation is complete.
- Care must be taken during the APB reset phase, because potentially the external clock (GCLK) may not present.
- During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST is cleared by hardware.