48.3 Power Supply

Table 48-6. Power Supply DC Electrical Specifications
DC CHARACTERISTICS			Standard Operating Conditions: VDDIO = AVDD 1.75V to 3.63V, VDDREG = 1.75V to 1.85V (unless otherwise stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	Min.	Typical	Max.	Units	Conditions
REG_5	VDDIO_CIN	VDDIO Input Bypass parallel Capacitor pair ⁽³⁾	33	—	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω ⁽³⁾
REG_5	VDDIO_CIN	VDDIO Input Bypass parallel Capacitor pair ⁽³⁾	100	—	—	nF	Ceramic X7R with ESR <0.5Ω on all VDDIOx pins ⁽³⁾
REG_6	VDDREG_CIN	VDDREG Input Bypass parallel Capacitor pair ⁽³⁾	33	—	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω ⁽³⁾
REG_6	VDDREG_CIN	VDDREG Input Bypass parallel Capacitor pair ⁽³⁾	100	—	—	nF	Ceramic X7R with ESR <0.5Ω on all VDDIOx pins ⁽³⁾
REG_10	VDDUSB_CIN	USB Power pin bypass capacitance ⁽³⁾	4.7	—	—	µF	Required VUSB3V3 power pin parallel bypass capacitors
REG_10	VDDUSB_CIN	USB Power pin bypass capacitance ⁽³⁾	0.1	—	—	µF	Required VUSB3V3 power pin parallel bypass capacitors
REG_17	AVDD_CIN	AVDD Input Bypass parallel Capacitor pair⁽³⁾	10	—	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_17	AVDD_CIN	AVDD Input Bypass parallel Capacitor pair⁽³⁾	100	—	—	nF	Ceramic X7R with ESR <0.5Ω
REG_23	AVDD_LEXT	AVDD series Ferrite Bead DCR (DC Resistance)	—	—	0.15	Ω	≥1kΩ @ 100 MHz
REG_25	AVDD_LEXT	Ferrite Bead current Rating	500	—	—	mA	—
REG_37	VDDIO⁽²⁾	VDDIO Input Voltage Range	1.75	3.3	3.63	V	—
REG_39	AVDD ⁽²⁾	AVDD Input Voltage Range	1.75	3.3	3.63	V	—
REG_40	VDDREG	VDDREG Input Voltage Range	1.75	1.8	1.85	V	—
REG_42	VUSB3V3	VUSB3V3 Input Voltage Range	3	—	3.6	V	—
REG_42A	IDDUSB	VUSB3V3 max current	—	—	8	mA	—
REG_43	SVDDIO_R	VDDIO Rise Ramp Rate to Ensure Internal Power-on Reset Signal	3.3 x 10(-7)	—	0.18	V/µs	Failure to meet this specification may lead to start-up or unexpected behaviors
REG_45	VP0R	Power-on Reset	1.447	—	1.573	V	VDDIO Power-up/Power-down (See Param REG43, VDDIO Ramp Rate)
REG_47	VDDIO BOR	VDDIO BOR	1.64	—	1.67	V	BOR_TRIP_VDDIO = 0x0 HYST_BOR_VDDIO = 0x0
			2.13	—	2.16	V	BOR_TRIP_VDDIO = 0x1 HYST_BOR_VDDIO = 0x0
			2.51	—	2.55	V	BOR_TRIP_VDDIO = 0x2 HYST_BOR_VDDIO = 0x0
			2.76	—	2.83	V	BOR_TRIP_VDDIO = 0x3 HYST_BOR_VDDIO = 0x0
			1.63	—	1.65	V	BOR_TRIP_VDDIO = 0x0 HYST_BOR_VDDIO = 0x1
			2.07	—	2.11	V	BOR_TRIP_VDDIO = 0x1 HYST_BOR_VDDIO = 0x1
			2.44	—	2.47	V	BOR_TRIP_VDDIO = 0x2 HYST_BOR_VDDIO = 0x1
			2.66	—	2.68	V	BOR_TRIP_VDDIO = 0x3 HYST_BOR_VDDIO = 0x1
REG_48	AVDD BOR	AVDD BOR	1.64	—	1.67	V	BOR_TRIP_VDDA = 0x0 HYST_BOR_VDDA = 0x0
			2.13	—	2.16	V	BOR_TRIP_VDDA = 0x1 HYST_BOR_VDDA = 0x0
			2.51	—	2.55	V	BOR_TRIP_VDDA = 0x2 HYST_BOR_VDDA = 0x0
			2.76	—	2.83	V	BOR_TRIP_VDDA = 0x3 HYST_BOR_VDDA = 0x0
			1.63	—	1.65	V	BOR_TRIP_VDDA = 0x0 HYST_BOR_VDDA = 0x1
			2.07	—	2.11	V	BOR_TRIP_VDDA = 0x1 HYST_BOR_VDDA = 0x1
			2.44	—	2.47	V	BOR_TRIP_VDDA = 0x2 HYST_BOR_VDDA = 0x1
			2.66	—	2.68	V	BOR_TRIP_VDDA = 0x3 HYST_BOR_VDDA = 0x1
REG_49	VDDREG BOR	VDDREG BOR	1.62	—	1.68	V	HYST_BOR_VDDREG = 0x0
REG_49	VDDREG BOR	VDDREG BOR	1.62	—	1.68	V	HYST_BOR_VDDREG = 0x1
REG_50	VDDUSB BOR	VDDUSB BOR	2.81	—	2.85	V	—
REG_53	TRST	External RESET valid active pulse width	2	—	—	µs	Minimum reset active time to guarantee MCU reset
Note: Ferrite Bead ISAT(min) ≥ (IDDANA(max) * 1.15). VDDIO and AVDD must be at the same voltage level. All bypass caps should be located immediately adjacent to pins and on the same side of the PCB as the MCU, or in the case of BGA packages, directly below the power pads and direct adjacent to the fan-out vias. Each primary power supply group VDDIO, and AVDD, should have one bulk capacitor and all power pins everywhere a 100 nf bypass cap.

PIC32CZ CA80/CA90 Family

48.3 Power Supply