Description
This Tcl command sets synthesis attribute to the specified SmartDesign module. The attribute is added in the HDL file at the component generation.
sd_set_comp_synth_attr \
-sd_name {SmartDesign component name} \
-attr_name {synthesis attribute name} \
-attr_value {synthesis attribute value}
Arguments
| Parameter | Type | Description |
|---|
| sd_name | string | This argument is used to specify the name of the SmartDesign module in which the synthesis attribute is set. This is a mandatory argument. |
| attr_name | string | This argument specifies the synthesis attribute. This is a mandatory argument. |
| attr_value | string | Value of the attribute. Some attributes do not require values. |
Synthesis Attributes
The following is the list of attributes and directives available in the Synopsys® FPGA synthesis tool that are supported by SmartDesign.
| Name |
Object |
Attribute/Directive |
| syn_insert_buffer |
port, instance |
Attribute |
| syn_keep |
net |
Directive |
| syn_maxfan |
port, net, instance, register |
Attribute |
| syn_no_compile_point |
module/architecture |
Attribute |
| syn_noclockbuf |
port, net, module/architecture |
Attribute |
| syn_noprune |
instance, module/architecture |
Directive |
| syn_preserve |
register, port, module/architecture |
Directive |
| Return Type | Description |
|---|
| None | None |
Error Codes
| Error Code | Description |
|---|
| None | Error: Failed to set synthesis attribute 'tlm_psioooc_eynn_pin' to component 'top'. This attribute cannot be set to components. |
| None | Parameter 'attr_value' has illegal value. |
| None | Required parameter 'attr_value' is missing. |
| None | Parameter 'attr_name' has illegal value. |
| None | Required parameter 'attr_name' is missing. |
| None | Parameter 'sd_name' has illegal value. |
| None | Required parameter 'sd_name' is missing. |
| None | Parameter 'param_name' is not defined. Valid command formatting is 'sd_set_comp_synth_attr -sd_name "sd_name" -attr_name "attr_name" -attr_value "attr_value"'. |
Supported Families
| Supported Families |
|---|
| PolarFire® |
| PolarFire SoC |
| RTG4™ |
| SmartFusion® 2 |
| IGLOO® 2 |
Example
This example sets "syn_no_compile_point" attribute with "false" value on the "top" component.
sd_set_comp_synth_attr -sd_name {top} \
-attr_name {syn_no_compile_point} \
-attr_value {false}
See Also
- sd_remove_comp_synth_attr
