16.3.26 ADC n Channel 2 Counter Register

Legend: n = ADC number; HS = Hardware Settable bit; HC = Hardware Clearable bit; R = Readable bit

Name:	ADnCH2CNT
Offset:	0x868, 0x968, 0xAE8


Bit	31	30	29	28	27	26	25	24
	CNTSTAT2[15:8]
Access	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	CNTSTAT2[7:0]
Access	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	CNT2[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CNT2[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:16 – CNTSTAT2[15:0]

Number of conversions done in integration (MODE[1:0] bits = ‘10’) and window (MODE[1:0] bits = ‘01’) sampling modes.

Bits 15:0 – CNT2[15:0]

Number of samples for an integration sampling mode (MODE[1:0] bits = ‘10’) and maximum number of samples for a window sampling mode (MODE[1:0] bits = ‘01’).