16.3.4 ADC n Result Ready Status Register

Legend: n = ADC number; HS = Hardware Settable bit; HC = Hardware Clearable bit

Name:	ADnRSTAT
Offset:	0x80C, 0x90C, 0xA8C


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	CH[7:0]RRDY
Access	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC
Reset	0	0	0	0	0	0	0	0

Bits 7:0 – CH[7:0]RRDY Channel x Conversion Result Ready bits

Each bit in this register is set by hardware when the corresponding channel x conversion result is written into the ADnRESx register. The bit is cleared by hardware when the ADnRESx register is read by software.