24.3.6 BiSS Control Communication Configuration Register
Note:
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With CLK = 20 MHz, clock frequencies ranging from 62.5 kHz to 10 MHz can be selected for sensor data transmission.
| Name: | B1CTRLCON |
| Offset: | 0x21E4 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| NOCRC | BANKSWEN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Reserved[2:0] | SFREQ[4:0] | ||||||||
| Access | R | R | R | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CTS | PROTOSEL | CMDCLNTID21[1:0] | IDADISCLNTID0 | MOEN | HOLDCDM | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHSEL[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 25 – NOCRC CRC for SCD Not to be Stored in RAM bit
| Value | Description |
|---|---|
| 1 | All client CRC of SCD is not stored in RAM. |
| 0 | CRC of SCD is stored in RAM (only applicable with active CRC verification and CRC polynomial > 0). |
Bit 24 – BANKSWEN Single RAM Bank Enabled bit
| Value | Description |
|---|---|
| 1 | One RAM bank is used for SCD. |
| 0 | Two RAM banks are used for SCD. |
Bits 23:21 – Reserved[2:0]
Bits 20:16 – SFREQ[4:0] Sensor Data Clock Frequency (FSCD) bits(1)
| Value | Description |
|---|---|
| 11111 - 10010 | CLK / 20 / (Value - 15) |
| 10001 | CLK / 40 |
| 10000 | Not permitted |
| 01111 - 00001 | CLK / 2 / (Value + 1) |
| 00000 | CLK/2 |
Bit 15 – CTS Register Transmission or Instruction Selector bit
| Value | Description |
|---|---|
| 1 | Register communication |
| 0 | Command/instruction communication |
Bit 14 – PROTOSEL Register Access Protocol Selection A/B or C Selector bit
| Value | Description |
|---|---|
| 1 | Register communication BiSS C |
| 0 | Reserved |
Bits 13:12 – CMDCLNTID21[1:0] CMD/CLNTID21 bit 1 and bit 2 – Command/Instruction bit in which the command is determined by Client/CLNTID21 Client ID of Accessed Client bit 1 and 2 onlyCMD and CLNTID21 share the same register location.
Bit 11 – IDADISCLNTID0 ID-Acknowledge Disable bit
| Value | Description |
|---|---|
| 1 | Immediate execution |
| 0 | The client’s feedback (IDA) is tested before execution (EX bit after IDA) |
Bit 9 – MOEN MO Enable - Enable Output at MOx for Actuator Data or Delayed Start bit
| Value | Description |
|---|---|
| 1 | Parameterized processing time by host when the MO signal is active (length = MODELAY). |
| 0 | MO is forced to low. |
Bit 8 – HOLDCDM Hold CDM (Control Data Host) - Length of CDM bit
| Value | Description |
|---|---|
| 1 | Clock line consistent with the CDM bit until start of the next cycle. |
| 0 | Clock line high at the end of cycle. |
Bits 7:0 – CHSEL[7:0] Channel Selection bits
| Value | Description |
|---|---|
| 1 | Channel N is used for communication. |
| 0 | Channel N is not used for communication. |