24.3.10 BiSS Instruction Register
| Name: | B1INSTR |
| Offset: | 0x21F4 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BREAK | BNKLOCK | SWBANK | INIT | INSTR[2:0] | AGS | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – BREAK Data Transmission Interrupt bit
| Value | Description |
|---|---|
| 1 | Abort data transmission |
| 0 | No change |
Bit 6 – BNKLOCK Inhibit RAM Bank Switching bit
| Value | Description |
|---|---|
| 1 | Bank switching lock |
| 0 | No bank switching lock |
Bit 5 – SWBANK Switch RAM Bank bit
| Value | Description |
|---|---|
| 1 | RAM banks are switched. |
| 0 | RAM banks are not switched. |
Bit 4 – INIT Start INIT Sequence bit
| Value | Description |
|---|---|
| 1 | Initialize data channel |
| 0 | No changes on the data channel |
Bits 3:1 – INSTR[2:0] SCD Control Instruction bits
Bit 0 – AGS Automatic Get Sensor Data bit
| Value | Description |
|---|---|
| 1 | Automatic data transmission |
| 0 | No automatic data transmission |