24.3.12 BiSS Configuration Register
Note:
- It is not recommended to set “
00” for CLKDIV bits. - Input to the CLKDIV depends on the CLKSEL value.
- The clock frequency (CLK) derived from CLKDIV must be maximum of 20 MHz.
| Name: | B1CON |
| Offset: | 0x21FC |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| INSTRWA | INSTRWE | REGAE | TXRDEN | SCDRST | REGRST | ||||
| Access | R | R/C | R/C | R/W | R/W | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CLKDIV[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | SLPEN | SIDL | CDM | CDS | SENSESEL | GETSENSE | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| REGACC | BNKNUM | ACTIVE | CLKSEL | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 31 – INSTRWA Instruction Write Active bit
| Value | Description |
|---|---|
| 1 | Previous write is not complete. |
| 0 | Previous write is complete. |
Bit 30 – INSTRWE Instruction Write Error bit
| Value | Description |
|---|---|
| 1 | Disallowed attempt to write Instruction register (must reset in software) |
| 0 | No instruction write error |
Bit 29 – REGAE Register Mode Data Access Error bit
| Value | Description |
|---|---|
| 1 | Disallowed attempt to access Register mode data (must reset in software) |
| 0 | No register access error |
Bit 26 – TXRDEN Transmit RAM CPU Read Enable bit
| Value | Description |
|---|---|
| 1 | Transmit RAM is allowed to read by CPU. |
| 0 | Receive RAM is allowed to read by CPU. |
Bit 25 – SCDRST SCD RAM Reset bit
1’
to reset the Register communication RAM data buffers.Reading this bit returns
‘1’ if the Register RAM is in Reset, and
‘0’ if Reset completed. Writing ‘0’ to
this bit has to come out of Reset when this bit is ‘1’,
otherwise writing ‘0’ to this bit has no
effect.
Bit 24 – REGRST Register RAM Reset bit
1’
to reset the Register communication RAM data buffers.Reading this bit returns
‘1’ if the Register RAM is in Reset, and
‘0’ if Reset completed. Writing ‘0’ to
this bit has to come out of Reset when this bit is ‘1’,
otherwise writing ‘0’ to this bit has no
effect.
Bits 23:16 – CLKDIV[7:0] Clock divider bits(1,2,3)
Bit 15 – ON Module Enable bit
| Value | Description |
|---|---|
| 1 | Module is enabled. |
| 0 | Module is disabled. |
Bit 13 – SLPEN Module Sleep Enable bit
| Value | Description |
|---|---|
| 1 | Module operates in Sleep mode. |
| 0 | Module disabled in Sleep mode. |
Bit 12 – SIDL Module Stop in Idle Mode Enable bit
| Value | Description |
|---|---|
| 1 | Module disabled in Idle mode. |
| 0 | Module operates in Idle mode. |
Bit 11 – CDM Control Data bit Host
| Value | Description |
|---|---|
| 1 | Host sends the control data bit (CDM). |
| 0 | Host has not sent the control data bit (CDM). |
Bit 10 – CDS Control Data bit Client
| Value | Description |
|---|---|
| 1 | Client sends the control data bit (CDS). |
| 0 | Client has not sent the control data bit (CDS). |
Bit 9 – SENSESEL Sense Selection bit
| Value | Description |
|---|---|
| 1 | Use external sense. |
| 0 | Use software sense. |
Bit 8 – GETSENSE Software Get-Sense bit
| Value | Description |
|---|---|
| 1 | Software data transmission is triggered. |
| 0 | Software data transmission is not triggered. |
Bit 4 – REGACC Register RAM Access Status bit
| Value | Description |
|---|---|
| 1 | BiSS Protocol Engine is accessing register RAM. |
| 0 | BiSS Protocol Engine is not accessing register RAM. |
Bit 3 – BNKNUM SCD RAM Access Status bit
| Value | Description |
|---|---|
| 1 | BiSS Protocol Engine is accessing RAM1. |
| 0 | BiSS Protocol Engine is accessing RAM2. |
Bit 2 – ACTIVE BiSS Active Status bit
| Value | Description |
|---|---|
| 1 | The BiSS module is active. |
| 0 | The BiSS module is inactive. |