16.4.1 PWM Clock Control Register
Note:
- These bits cannot be modified
while PCLKCON.LOCK =
1. - These bits are not present
when FEP =
0. - User software may write a ‘0’ (after the bit has been set earlier) to this location to turn off and then on the FEP macro. This will force the FEP macro to attempt a new calibration.
- These bits cannot be cleared by clearing the HREN bit. If it has been set prior to clearing the HREN bit, it has to be cleared manually prior to entering high-resolution operation.
- The PWM clock will also be connected to the clock generator 5 to support the FEP. When FEP is selected, the MCLKSEL control bits must be set to select the clock generator. Otherwise, unexpected results will occur.
| Name: | PCLKCON |
| Offset: | 0x1000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| HRRDY | HRERR | LOCK | |||||||
| Access | R | R/C | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIVSEL[1:0] | Reserved | MCLKSEL | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 1 | 0 | |||||
Bit 15 – HRRDY High-Resolution Ready bit(2)
| Value | Description |
|---|---|
1 |
The high-resolution circuitry is ready. |
0 |
The high-resolution circuitry is not ready. |
Bit 14 – HRERR High-Resolution Error bit(2,3,4)
| Value | Description |
|---|---|
1 |
An error has occurred during fine edge placement. If allowed to proceed, PWM signals will have limited resolution (FEP operates without the high-resolution capability). |
0 |
No error has
occurred. PWM signals will have full resolution when HRRDY =
1. |
Bit 8 – LOCK Lock bit
| Value | Description |
|---|---|
1 |
Write-protected registers and bits are locked. |
0 |
Write-protected registers and bits are unlocked. |
Bits 5:4 – DIVSEL[1:0] PWM Clock Divider Selection bits(1)
| Value | Description |
|---|---|
11 |
Divide ratio is 1:16. |
10 |
Divide ratio is 1:8. |
01 |
Divide ratio is 1:4 |
00 |
Divide ratio is 1:2 |
Bit 2 – Reserved
Reserved; maintain as '1'.
Bit 0 – MCLKSEL PWM Master Clock Selection bit(1,5)
Note: Do not change the
MCLKSEL bit while PGxCON.ON =
1.Note: See Table 16-3 for MCLKSEL selections.
| Value | Description |
|---|---|
| 1 | CKLGEN5 |
| 0 | UPB clock (1:2 of CPU clock) |