16.4.5 Master Duty Cycle Register

Note:

These bits cannot be modified while UPDATE = 1.
If HREN = 0, the four least significant bits are read as ‘0000’.

Name:	MDC
Offset:	0x1010


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
					MDC[19:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8
	MDC[19:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	MDC[19:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 19:0 – MDC[19:0] Master Duty Cycle Register bits^(1,2)

This register holds the duty cycle value that can be shared by multiple PWM Generators.

Note: Duty cycle values less than 0x0010 should not be used.

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