16.4.50 Auxiliary PWM Generator x Control Register
- These bits cannot be modified
while PGxCON.ON =
1. - Caution should be used when modifying bits while PGxCON.ON =
1; unexpected results may occur. - Any generator can be used to trigger any other generator.
- When this bit is cleared, an asynchronous reset is initiated, causing all of the macro outputs to return to their reset/default states, which can appear as glitches. Safe shutdown procedures are highly recommended to ensure all recipients of these glitches enter their benign states prior to this bit being cleared.
- This bit is not present when
FEP =
0. - The PCI selected sync signal is always available to be “OR’d” with the selected SOCx signal per the SOCS[3:0] if the PCI sync function is enabled.
- The source selected by the SOCS[3:0] bits MUST operate from the same clock source as the PWM generator. If not, the source must be routed through the PCI Sync logic so the trigger signal can be synchronized to the PWM generator clock domain.
- The PWM generator timebase operates from the Frequency Scaling circuit clock, effectively scaling the duty cycle and period of the PWM generator output. The remainder of the PWM circuit operates from the clock source supplied to the Frequency Scaling circuit.
- This clock source should not be used when PGxCON.HREN =
1; unexpected results may occur. - These bits cannot be modified while PCLKCON.LOCK =
1.
| Name: | APGxCON |
| Offset: | 0x1438, 0x14AC, 0x1520, 0x1594 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| MDCSEL | MPERSEL | MPHSEL | MSTEN | UPDMOD[2:0] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TRGMOD[1:0] | SOCS[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | TRGCNT[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLKSEL[1:0] | MODSEL[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 31 – MDCSEL Master Duty Cycle Register Select bit(2)
| Value | Description |
|---|---|
1 |
PWM Generator uses the MDC register. |
0 |
PWM Generator uses the PGxDC register. |
Bit 30 – MPERSEL Master Period Register Select bit(2)
| Value | Description |
|---|---|
1 |
PWM Generator uses the MPER register. |
0 |
PWM Generator uses the PGxPER register. |
Bit 29 – MPHSEL Master Phase Register Select bit (2)
| Value | Description |
|---|---|
1 |
PWM Generator uses the MPHASE register. |
0 |
PWM Generator uses the PGxPHASE register. |
Bit 27 – MSTEN Master Update Enable bit(2)
| Value | Description |
|---|---|
1 |
PWM Generator broadcasts software set of the UPDREQ control bit and EOC signal to other PWM Generators. |
0 |
PWM Generator does not broadcast the UPDREQ status bit state or EOC signal. |
Bits 26:24 – UPDMOD[2:0] PWM Buffer Update Mode Selection bits
See Table 16-11 for details.
Bits 23:22 – TRGMOD[1:0] PWM Generator x Trigger Mode Selection bits(2)
| Value | Description |
|---|---|
| 11 | Reserved |
| 10 | Reserved |
| 01 | PWM Generator operates in Retriggerable mode. |
| 00 | PWM Generator operates in Single Trigger mode. |
Bits 19:16 – SOCS[3:0] Start-of-Cycle Selection bits(2,3,6,7)
| Value | Description |
|---|---|
| 1111-0101 |
TRIG bit or PCI Sync function only (no hardware trigger source selected). |
| 0100 | PWM4 PG Trigger output selected by PG4 PGTRGSEL[2:0] bits (PG4EVT[2:0]). |
| 0011 | PWM3 PG Trigger output selected by PG3 PGTRGSEL[2:0] bits (PG3EVT[2:0]). |
| 0010 | PWM2 PG Trigger output selected by PG2 PGTRGSEL[2:0] bits (PG2EVT[2:0]). |
| 0001 | PWM1 PG Trigger output selected by PG1 PGTRGSEL[2:0] bits (PG1EVT[2:0]). |
| 0000 | Local EOC - PWM Generator is self-triggered. |
Bit 15 – ON PWM Generator x Enable bit(4)
| Value | Description |
|---|---|
1 |
PWM Generator is enabled. |
0 |
PWM Generator is not enabled. |
Bits 10:8 – TRGCNT[2:0] PWM Generator x Trigger Count Select bits(1)
| Value | Description |
|---|---|
111 |
PWM Generator produces 8 PWM cycles after triggered. |
110 |
PWM Generator produces 7 PWM cycles after triggered. |
101 |
PWM Generator produces 6 PWM cycles after triggered. |
100 |
PWM Generator produces 5 PWM cycles after triggered. |
011 |
PWM Generator produces 4 PWM cycles after triggered. |
010 |
PWM Generator produces 3 PWM cycles after triggered. |
001 |
PWM Generator produces 2 PWM cycles after triggered. |
000 |
PWM Generator produces 1 PWM cycle after triggered. |
Bits 4:3 – CLKSEL[1:0] Clock Selection bits(2)
- Do not change the CLKSEL[1:0]
bits while ON (PGxCON[15]) =
1. - The PWM Generator time base operates from the frequency scaling circuit clock, effectively scaling the duty cycle and period of the PWM Generator output.
| Value | Description |
|---|---|
11 |
PWM Generator uses the master clock scaled by the frequency scaling circuit(8,9). |
10 |
PWM Generator uses the master clock divided by the clock divider circuit(9). |
01 |
PWM Generator uses the master clock selected by the MCLKSEL[1:0] (PCLKCON[1:0]) control bits. |
00 |
No clock selected, PWM Generator is in the lowest power state (default). |
Bits 2:0 – MODSEL[2:0] PWM Generator x Mode Selection bits(1)
| Value | Description |
|---|---|
111 |
Dual Edge Center-Aligned PWM mode (interrupt/register update twice per cycle) |
110 |
Dual Edge Center-Aligned PWM mode (interrupt/register update once per cycle) |
101 |
Double Update Center-Aligned PWM mode |
100 |
Center-Aligned PWM mode |
011 |
LLC Resonant Converter Support PWM mode |
010 |
Independent Edge PWM mode, dual output |
001 |
Variable Phase PWM mode |
000 |
Independent Edge PWM mode |