16.4.43 Auxiliary PWM Master Phase Register

Note:

These bits cannot be modified while UPDATE = 1.
If HREN = 0, the four least significant bits are read as ‘0000’.

Name:	AMPHASE
Offset:	0x140C


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
					MPHASE[19:16]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8
	MPHASE[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	MPHASE[7:4]
Access	R/W	R/W	R/W	R/W
Reset	0	0	0	0

Bits 19:16 – MPHASE[19:16]

Bits 15:8 – MPHASE[15:8]

Bits 7:4 – MPHASE[7:4] Master Phase Register bits^(1,2)

This register holds the phase offset value that can be shared by multiple PWM Generators.

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