16.4.49 Auxiliary PWM Event Output Control Register
Note:
- ‘y’ denotes a common instance (A-F).
- This is the PWM generator output signal prior to output mode logic and any output override logic.
- Event output signal pulse will be two system clocks when this bit is set and
EVTySTRD =
1. - The event signal is stretched using peripheral bus clock because different PWM Generators may be operating from different clock sources.
| Name: | APWMEVTy |
| Offset: | 0x1428, 0x142C, 0x1430, 0x1434 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EVTyOEN | EVTyPOL | EVTySTRD | EVTySYNC | EVTyPGS[2:0] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EVTySEL[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 15 – EVTyOEN PWM Event Output Enable bit
| Value | Description |
|---|---|
1 |
Event output signal is output on the PWMEy pin |
0 |
Event output signal is internal only |
Bit 14 – EVTyPOL PWM Event Output Polarity bit
| Value | Description |
|---|---|
1 |
Event output signal is active-low |
0 |
Event output signal is active-high |
Bit 13 – EVTySTRD PWM Event Output Stretch Disable bit(4)
| Value | Description |
|---|---|
1 |
Event output signal pulse width is not stretched |
0 |
Event output signal is stretched to eight PWM clock cycles minimum |
Bit 12 – EVTySYNC PWM Event Output Sync bit(3)
Event output signal pulse will be synchronized to peripheral_clk.
| Value | Description |
|---|---|
1 |
Event output signal is synchronized to the system clock |
0 |
Event output is not synchronized to the system clock |
Bits 10:8 – EVTyPGS[2:0] PWM Event Source Selection bits
| Value | Description |
|---|---|
| 111-100 | Reserved |
| 011 | PG4 |
| 010 | PG3 |
| 001 | PG2 |
| 000 | PG1 |
Bits 4:0 – EVTySEL[4:0] PWM Event Selection bits(2)
| Value | Description |
|---|---|
| 11111-01100 | Reserved |
| 01011 | DAC Trigger signal |
| 01010 | ADC Trigger 2 signal |
| 01001 | ADC Trigger 1 signal |
| 01000 | STEER signal (available in Push-Pull Output modes only) |
| 00111 | PHASE signal (available in Center Aligned modes only) |
| 00110 | PCI Fault2 Active Output signal |
| 00101 | PCI Fault1 Active Output signal |
| 00100 |
PCI Current Limit Active Output signal |
| 00011 |
PCI Feed-Forward Active Output signal |
| 00010 |
PCI Sync Active Output signal |
| 00001 |
PWM Generator Output signal |
| 00000 |
Source is selected by the PGTRGSEL[2:0] bits. |