16.4.18 PWM Generator x F1 PCI 2 Register

Note:
  1. Caution should be used when modifying register bits while PGxCON.ON = 1; unexpected results may occur.
  2. If more than one bit is set, the selected PCI sources are OR’ed together.
  3. If the PCI software control has a higher priority than PSS, if SWPCIM[1:0] = 2’b00 and SWPCI = 1’b1, a PCI event is generated regardless of PSS[31:0] content.
Name: PGxF1PCI2
Offset: 0x106C, 0x10E0, 0x1154, 0x11C8, 0x123C, 0x12B0, 0x1324, 0x1398

Bit 3130292827262524 
 PSS[31:24] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 PSS[23:16] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 PSS[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 PSS[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 31:0 – PSS[31:0]  PCI Source Selection bits(1,2,3)

Refer to Table 16-4 for device-specific PSS bit information.