16.3.22 ADC 2 Channel n Secondary
Accumulator Register
Legend:n = ADC channel number (6-7); R = Readable bit
Name:
AD2CHnACC
Offset:
0x0AF4,
0x0B14
Bit
31
30
29
28
27
26
25
24
ACC[31:24]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
ACC[23:16]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
ACC[15:8]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ACC[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – ACC[31:0] Secondary
Accumulator bits
DS70005591D
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
