16.3.39 ADC 5 Channel n Control Register 1

Note:

These bits are used with Oversampling mode only when MODE[1:0] bits = ‘11’ and are ignored for all other sampling modes.
For the correct operation, this bit must be used only for the triggers TRG1SRC[5:0] = ‘00100’ - ‘11111’.
Early interrupts are only available for single sample operations (MODE[1:0] bits = ‘00’). Multisample operations ignore the EIEN bit and use normal interrupt timing.
Do not use an early interrupt if using DMA transfers; the data might not be ready. The early interrupt is asserted at the start of sampling.

Legend: n = ADC channel number (0-15); R = Readable bit; W = Writable bit

Name:	AD5CHnCON1
Offset:	0x0D98, 0xDB8, 0xDD8, 0xDF8, 0xE18, 0xE38, 0xE58, 0xE78, 0xE98, 0xEB8, 0xED8, 0xEF8, 0xF18, 0xF38, 0xF58, 0xF78

Bit 31 – DIFF Differential Input Enable bit

Value	Description
1	Differential Input mode; data are output as signed (two’s complement).
0	Single Ended Input mode; data are output as unsigned.

Value	Description
1	Result in ADxCHxDATA and ADxCHnRES registers are aligned to the left (in the fractional format).
0	Result in ADxCHxDATA and ADxCHnRES registers are aligned to the right.

The value of NINSEL[1:0] selects the negative analog input in the format ADxANNn, where x is the ADC instance and n is the NINSEL[1:0] value.

Examples:

Refer to ADC Input Availability for the available negative analog inputs.

The value of PINSEL[3:0] selects the positive analog input in the format ADxANn, where x is the ADC instance and n is the PINSEL[3:0] value.

Examples:

Refer to ADC Input Availability for the available positive analog inputs.

Value	Description
1	Active level of the signal selected by TRG1SRC[5:0] bits, is low; a falling edge generates a conversion request.
0	Active level of the signal selected by TRG1SRC[5:0] bits is high; a rising edge generates a conversion request.

Value	Description
1	Early interrupt is enabled.
0	Normal interrupt timing

Value	Description
1	The channel interrupt is generated when data is ready in the ADxCHnDATA register.
0	The channel interrupt is generated after each single conversion when result is ready in ADxCHnRES register.

Value	Description
11	256 samples, 16 bits result in ADxCHnDATA register
10	64 samples, 15 bits result in ADxCHnDATA register
01	16 samples, 14 bits result in ADxCHnDATA register
00	Four samples, 13 bits result in ADxCHnDATA register

Value	Description
11	Oversampling of multiple samples defined by ACCNUM[1:0] bits. The first conversion is initiated by the TRG1SRC[5:0] trigger and all other conversions are executed by the TRG2SRC[5:0] trigger
10	Integration of multiple samples defined by: CNTx[15:0] bits (ADxCNTn[15:0]). The first conversion is initiated by the TRG1SRC[5:0] trigger and all other conversions are executed by the TRG2SRC[5:0] trigger.
01	Window gated by TRG1SRC[5:0] source. In this mode the samples are accumulated when a signal selected by the TRG1SRC[5:0] bits has an active level. All conversions are initiated by the TRG2SRC[5:0] trigger. The number of conversions is limited by CNTx[15:0] bits (ADxCNTn[15:0])
00	Single sample initiated by TRG1SRC[5:0] trigger.