16.3.43 ADC 5 Channel n Counter Register

Legend: n = ADC channel number (0-15); HS = Hardware Settable bit; HC = Hardware Clearable bit; R = Readable bit; W = Writable bit

Name:	AD5CHnCNT
Offset:	0xDA8, 0xDC8, 0xDE8, 0xE08, 0xE28, 0xE48, 0xE68, 0xE88, 0xEA8, 0xEC8, 0xEE8, 0xF08, 0xF28, 0xF48, 0xF68, 0xF88


Bit	31	30	29	28	27	26	25	24
	CNTSTAT[15:8]
Access	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	CNTSTAT[7:0]
Access	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	CNT[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CNT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:16 – CNTSTAT[15:0] Channel Conversion Count bits

Number of conversions done in Integration (MODE[1:0] bits = ‘10’) and Window (MODE[1:0] bits = ‘01’) Sampling modes.

Bits 15:0 – CNT[15:0] Channel Sample Count bits

Number of samples for an Integration Sampling mode (MODE[1:0] bits = ‘10’) and maximum number of samples for a Window Sampling mode (MODE[1:0] bits = ‘01’).