63.10.49 SPI FIFO Mode Register

This register reads ‘0’ if the FIFO is disabled (see FLEX_SPI_CR to enable/disable the internal FIFO)
Name: FLEX_SPI_FMR
Offset: 0x440
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
   RXFTHRES[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 2322212019181716 
   TXFTHRES[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
   RXRDYM[1:0]  TXRDYM[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 29:24 – RXFTHRES[5:0] Receive FIFO Threshold

ValueDescription
0–32 Defines the Receive FIFO threshold value (number of data). The FLEX_SPI_SR.RXFTH flag will be set when Receive FIFO goes from “below” threshold state to “equal to or above” threshold state.

Bits 21:16 – TXFTHRES[5:0] Transmit FIFO Threshold

ValueDescription
0–32 Defines the Transmit FIFO threshold value (number of data). The FLEX_SPI_SR.TXFTH flag will be set when Transmit FIFO goes from “above” threshold state to “equal to or below” threshold state.

Bits 5:4 – RXRDYM[1:0] Receive Data Register Full Mode

If FIFOs are enabled, the FLEX_SPI_SR.RDRF flag behaves as follows.

ValueNameDescription
0 ONE_DATA

RDRF will be at level ‘1’ when at least one unread data is in the receive FIFO.

When DMA is enabled to transfer data and FLEX_SPI_CSR0.BITS=0 (8 bits transfered on SPI line), the chunk of 1 byte must be configured in the DMA.

When FLEX_SPI_CSR0.BITS>0 (9 to 16 bits transfered on SPI line), the chunk of 1 halfword must be configured in the DMA.

If the transfer is performed by software, the access type can be defined as byte or halfword depending on FLEX_SPI_CSR0.BITS.

1 TWO_DATA

RDRF will be at level ‘1’ when at least two unread data are in the receive FIFO.

To minimize system bus load, when DMA is enabled to transfer data and FLEX_SPI_CSR0.BITS=0 (8 bits transfered on SPI line), the chunk of 1 halfword (1 halfword carries 2 bytes) must be configured in the DMA. When FLEX_SPI_CSR0.BITS>0 (9 to 16 bits transfered on SPI line), the chunk of 1 word (1 word carries 2 halfwords) must be configured in the DMA.

If the transfer is performed by software, the access type can be defined as halfword (2 bytes per access, 1 access when FLEX_SPI_CSR0.BITS=0), or word (2 halfwords per access, 2 accesses when FLEX_SPI_CSR0.BITS>0).

2 FOUR_DATA

RDRF will be at level ‘1’ when at least four unread data are in the receive FIFO.

To minimize system bus load, when DMA is enabled to transfer data and FLEX_SPI_CSR0.BITS=0 (8 bits transfered on SPI line), the chunk of 1 word (1 halfword carries 4 bytes) must be configured in the DMA. When FLEX_SPI_CSR0.BITS>0 (9 to 16 bits transfered on SPI line), the chunk of 2 words (1 word carries 4 bytes) must be configured in the DMA.

If the transfer is performed by software, the access type can be defined as word (4 bytes per access, 1 access when FLEX_SPI_CSR0.BITS=0 or 2 halfwords per access, 2 accesses when FLEX_SPI_CSR0.BITS>0).

Bits 1:0 – TXRDYM[1:0] Transmit Data Register Empty Mode

If FIFOs are enabled, the FLEX_SPI_SR.TDRE flag behaves as follows.

ValueNameDescription
0 ONE_DATA

TDRE will be at level ‘1’ when at least one data can be written in the transmit FIFO.

When DMA is enabled to transfer data, the chunk of 1 data (byte or halfword) must be configured in the DMA depending on FLEX_SPI_CSR0.BITS.

If the transfer is performed by software, the access type (byte, halfword) must be defined depending on FLEX_SPI_CSR0.BITS.

1 TWO_DATA

TDRE will be at level ‘1’ when at least two data can be written in the transmit FIFO.

FIFO.

To minimize system bus load, when DMA is enabled to transfer data, the chunk of 1 word (1 word carries 2 data) must be configured in the DMA.

If the transfer is performed by software, the access type must be defined as word (2 data per access, 1 access).