63.10.44 SPI Status Register

Name: FLEX_SPI_SR
Offset: 0x410
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
 RXFPTEFTXFPTEFRXFTHFRXFFFRXFEFTXFTHFTXFFFTXFEF 
Access RRRRRRRR 
Reset 00000000 
Bit 2322212019181716 
        SPIENS 
Access R 
Reset 0 
Bit 15141312111098 
    SFERRCMPUNDESTXEMPTYNSSR 
Access RRRRR 
Reset 00000 
Bit 76543210 
     OVRESMODFTDRERDRF 
Access RRRR 
Reset 0000 

Bit 31 – RXFPTEF Receive FIFO Pointer Error Flag

See FIFO Pointer Error for details.

This bit reads ‘0’ if the FIFO is disabled (see FLEX_SPI_CR to enable/disable the internal FIFO).

ValueDescription
0 No Receive FIFO pointer occurred.
1 Receive FIFO pointer error occurred. The receiver must be reset.

Bit 30 – TXFPTEF Transmit FIFO Pointer Error Flag

See FIFO Pointer Error for details.

This bit reads ‘0’ if the FIFO is disabled (see FLEX_SPI_CR to enable/disable the internal FIFO).

ValueDescription
0 No Transmit FIFO pointer occurred.
1 Transmit FIFO pointer error occurred. The transceiver must be reset.

Bit 29 – RXFTHF Receive FIFO Threshold Flag

This bit reads ‘0’ if the FIFO is disabled (see FLEX_SPI_CR to enable/disable the internal FIFO).
ValueDescription
0 Number of unread data in Receive FIFO is below RXFTHRES threshold or RXFTH flag has been cleared.
1 Number of unread data in Receive FIFO has reached RXFTHRES threshold (changing states from “below threshold” to “equal to or above threshold”).

Bit 28 – RXFFF Receive FIFO Full Flag

This bit reads ‘0’ if the FIFO is disabled (see FLEX_SPI_CR to enable/disable the internal FIFO).
ValueDescription
0 Receive FIFO is not empty or RXFE flag has been cleared.
1 Receive FIFO has been filled (changing states from “not full” to “full”).

Bit 27 – RXFEF Receive FIFO Empty Flag

This bit reads ‘0’ if the FIFO is disabled (see FLEX_SPI_CR to enable/disable the internal FIFO).
ValueDescription
0 Receive FIFO is not empty or RXFE flag has been cleared.
1 Receive FIFO has been emptied (changing states from “not empty” to “empty”).

Bit 26 – TXFTHF Transmit FIFO Threshold Flag (cleared on read)

This bit reads ‘0’ if the FIFO is disabled (see FLEX_SPI_CR to enable/disable the internal FIFO).
ValueDescription
0 Number of data in Transmit FIFO is above TXFTHRES threshold.
1 Number of data in Transmit FIFO has reached TXFTHRES threshold since the last read of FLEX_SPI_SR.

Bit 25 – TXFFF Transmit FIFO Full Flag (cleared on read)

This bit reads ‘0’ if the FIFO is disabled (see FLEX_SPI_CR to enable/disable the internal FIFO).
ValueDescription
0 Transmit FIFO is not full or TXFF flag has been cleared.
1 Transmit FIFO has been filled since the last read of FLEX_SPI_SR.

Bit 24 – TXFEF Transmit FIFO Empty Flag (cleared on read)

This bit reads ‘0’ if the FIFO is disabled (see FLEX_SPI_CR to enable/disable the internal FIFO).
ValueDescription
0 Transmit FIFO is not empty.
1 Transmit FIFO has been emptied since the last read of FLEX_SPI_SR.

Bit 16 – SPIENS SPI Enable Status

ValueDescription
0 SPI is disabled.
1 SPI is enabled.

Bit 12 – SFERR Client Mode Frame Error (cleared on read)

ValueDescription
0 No frame error has been detected for a client access since the last read of FLEX_SPI_SR.
1 In Client mode, the chip select raised while the character defined in FLEX_SPI_CSR0.BITS was not complete.

Bit 11 – CMP Comparison Status (cleared on read)

ValueDescription
0 No received character matched the comparison criteria programmed in VAL1 and VAL2 fields in FLEX_SPI_CMPR since the last read of FLEX_SPI_SR.
1 A received character matched the comparison criteria since the last read of FLEX_SPI_SR.

Bit 10 – UNDES Underrun Error Status (Client mode only) (cleared on read)

ValueDescription
0 No underrun has been detected since the last read of FLEX_SPI_SR.
1 A transfer starts whereas no data has been loaded in FLEX_SPI_TDR, cleared when FLEX_SPI_SR is read.

Bit 9 – TXEMPTY Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)

ValueDescription
0 As soon as data is written in FLEX_SPI_TDR.
1 FLEX_SPI_TDR and internal shift register are empty. If a transfer delay has been defined, TXEMPTY is set after the end of this delay.

Bit 8 – NSSR NSS Rising (cleared on read)

ValueDescription
0 No rising edge detected on NSS pin since the last read of FLEX_SPI_SR.
1 A rising edge occurred on NSS pin since the last read of FLEX_SPI_SR.

Bit 3 – OVRES Overrun Error Status (cleared on read)

An overrun occurs when FLEX_SPI_RDR is loaded at least twice from the shift register since the last read of FLEX_SPI_RDR.

ValueDescription
0 No overrun has been detected since the last read of FLEX_SPI_SR.
1 An overrun has occurred since the last read of FLEX_SPI_SR.

Bit 2 – MODF Mode Fault Error (cleared on read)

ValueDescription
0 No mode fault has been detected since the last read of FLEX_SPI_SR.
1 A mode fault occurred since the last read of FLEX_SPI_SR.

Bit 1 – TDRE Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)

When FIFOs are disabled:

0: Data has been written to FLEX_SPI_TDR and not yet transferred to the internal shift register.

1: The last data written to FLEX_SPI_TDR has been transferred to the internal shift register.

TDRE is cleared when the SPI is disabled or at reset. Enabling the SPI sets the TDRE flag.

When FIFOs are enabled:

0: Transmit FIFO cannot accept more data.

1: Transmit FIFO can accept data; one or more data can be written according to TXRDYM field configuration.

TDRE behavior with FIFOs enabled is illustrated in TXEMPTY, TDRE and RDRF Behavior.

Bit 0 – RDRF Receive Data Register Full (cleared by reading FLEX_SPI_RDR)

When FIFOs are disabled:

0: No data has been received since the last read of FLEX_SPI_RDR.

1: Data has been received and the received data has been transferred from the internal shift register to FLEX_SPI_RDR since the last read of FLEX_SPI_RDR.

When FIFOs are enabled:

0: Receive FIFO is empty; no data to read.

1: At least one unread data is in the Receive FIFO.

RDRF behavior with FIFOs enabled is illustrated in TXEMPTY, TDRE and RDRF Behavior.