63.10.77 TWI FIFO Status Register

This register reads ‘0’ if the FIFO is disabled (see FLEX_TWI_CR to enable/disable the internal FIFO)
Name: FLEX_TWI_FSR
Offset: 0x660
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 RXFPTEFTXFPTEFRXFTHFRXFFFRXFEFTXFTHFTXFFFTXFEF 
Access RRRRRRRR 
Reset 00000000 

Bit 7 – RXFPTEF Receive FIFO Pointer Error Flag

See FIFO Pointer Error for details.

ValueDescription
0

No Receive FIFO pointer occurred.
1

Receive FIFO pointer error occurred. Receiver must be reset.

Bit 6 – TXFPTEF Transmit FIFO Pointer Error Flag

See FIFO Pointer Error for details.

ValueDescription
0

No Transmit FIFO pointer occurred.
1

Transmit FIFO pointer error occurred. Transceiver must be reset.

Bit 5 – RXFTHF Receive FIFO Threshold Flag

ValueDescription
0

Number of unread data in Receive FIFO is below RXFTHRES threshold.
1

Number of unread data in Receive FIFO has reached RXFTHRES threshold since the last read of FLEX_TWI_FSR.

Bit 4 – RXFFF Receive FIFO Full Flag

ValueDescription
0

Receive FIFO is not empty.
1

Receive FIFO has been filled since the last read of FLEX_TWI_FSR.

Bit 3 – RXFEF Receive FIFO Empty Flag

ValueDescription
0

Receive FIFO is not empty.
1

Receive FIFO has been emptied since the last read of FLEX_TWI_FSR.

Bit 2 – TXFTHF Transmit FIFO Threshold Flag (cleared on read)

ValueDescription
0

Number of data in Transmit FIFO is above TXFTHRES threshold.
1

Number of data in Transmit FIFO has reached TXFTHRES threshold since the last read of FLEX_TWI_FSR.

Bit 1 – TXFFF Transmit FIFO Full Flag (cleared on read)

ValueDescription
0

Transmit FIFO is not full.
1

Transmit FIFO has been filled since the last read of FLEX_TWI_FSR.

Bit 0 – TXFEF Transmit FIFO Empty Flag (cleared on read)

ValueDescription
0

Transmit FIFO is not empty.
1

Transmit FIFO has been emptied since the last read of FLEX_TWI_FSR.