63.10.18 USART Baud Rate Generator Register

This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.

Name: FLEX_US_BRGR
Offset: 0x220
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
      FP[2:0] 
Access R/WR/WR/W 
Reset 000 
Bit 15141312111098 
 CD[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 CD[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 18:16 – FP[2:0] Fractional Part

Warning: When the value of field FP is greater than 0, the SCK (oversampling clock) generates nonconstant duty cycles. The SCK high duration is increased by “selected clock” period from time to time. The duty cycle depends on the value of the CD field.
ValueDescription
0

Fractional divider is disabled.

1–7

Baud rate resolution, defined by FP × 1/8.

Bits 15:0 – CD[15:0] Clock Divider

CD USART_MODE ≠

ISO7816

USART_MODE = ISO7816

SYNC = 0

SYNC = 1
OVER = 0 OVER = 1
0 Baud Rate Clock disabled
1 to 65535 CD = Selected Clock / (16 × Baud Rate) CD = Selected Clock / (8 × Baud Rate) CD = Selected Clock / Baud Rate CD = Selected Clock / (FI_DI_RATIO × Baud Rate)