63.10.18 USART Baud Rate Generator Register
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
| Name: | FLEX_US_BRGR |
| Offset: | 0x220 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FP[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CD[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CD[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 18:16 – FP[2:0] Fractional Part
Warning: When the value of field FP is greater than 0, the SCK (oversampling
clock) generates nonconstant duty cycles. The SCK high duration is increased by
“selected clock” period from time to time. The duty cycle depends on the value of the
CD field.
| Value | Description |
|---|---|
| 0 | Fractional divider is disabled. |
| 1–7 | Baud rate resolution, defined by FP × 1/8. |
Bits 15:0 – CD[15:0] Clock Divider
| CD | USART_MODE ≠
ISO7816 |
USART_MODE = ISO7816 | ||
|---|---|---|---|---|
|
SYNC = 0 |
SYNC = 1 | |||
| OVER = 0 | OVER = 1 | |||
| 0 | Baud Rate Clock disabled | |||
| 1 to 65535 | CD = Selected Clock / (16 × Baud Rate) | CD = Selected Clock / (8 × Baud Rate) | CD = Selected Clock / Baud Rate | CD = Selected Clock / (FI_DI_RATIO × Baud Rate) |