63.10.10 USART Interrupt Mask Register (Default
Mode)
For LIN-specific
configurations, see USART Interrupt Mask Register
(LIN_MODE).
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
| Name: | FLEX_US_IMR (DEFAULT_MODE) |
| Offset: | 0x210 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | MANE | |
| Access | | | | | | | | R | |
| Reset | | | | | | | | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | CMP | | | CTSIC | | | | |
| Access | | R | | | R | | | | |
| Reset | | 0 | | | 0 | | | | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | NACK | | | ITER | TXEMPTY | TIMEOUT | |
| Access | | | R | | | R | R | R | |
| Reset | | | 0 | | | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | PARE | FRAME | OVRE | | | RXBRK | TXRDY | RXRDY | |
| Access | R | R | R | | | R | R | R | |
| Reset | 0 | 0 | 0 | | | 0 | 0 | 0 | |
Bit 24 – MANE Manchester Error Interrupt Mask
Bit 22 – CMP Comparison Interrupt Mask
Bit 19 – CTSIC Clear to Send Input Change Interrupt Mask
Bit 13 – NACK Non Acknowledge Interrupt Mask
Bit 10 – ITER Max Number of Repetitions Reached Interrupt Mask
Bit 9 – TXEMPTY TXEMPTY Interrupt Mask
Bit 8 – TIMEOUT Timeout Interrupt Mask
Bit 7 – PARE Parity Error Interrupt Mask
Bit 6 – FRAME Framing Error Interrupt Mask
Bit 5 – OVRE Overrun Error Interrupt Mask
Bit 2 – RXBRK Receiver Break Interrupt Mask
Bit 1 – TXRDY TXRDY Interrupt Mask
Bit 0 – RXRDY RXRDY Interrupt Mask
