63.10.61 TWI Status Register (FIFO ENABLED)
If FIFO is enabled (FLEX_US_CR.FIFOEN bit), see TWI Multiple Data Access for details.
| Name: | FLEX_TWI_SR (FIFO_ENABLED) |
| Offset: | 0x620 |
| Reset: | 0x0300F009 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SR | SDA | SCL | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 1 | 1 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TXFLOCK | SMBHHM | SMBDAM | PECERR | TOUT | SMBAF | MCACK | |||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EOSACC | SCLWS | ARBLST | NACK | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UNRE | OVRE | GACC | SVACC | SVREAD | TXRDY | RXRDY | TXCOMP | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
Bit 26 – SR Start Repeated
| Value | Description |
|---|---|
| 0 | No repeated start has been detected since last FLEX_TWI_SR read. |
| 1 | At least one repeated start has been detected since last FLEX_TWI_SR read. |
Bit 25 – SDA SDA Line Value
| Value | Description |
|---|---|
| 0 | SDA line sampled value is ‘0’. |
| 1 | SDA line sampled value is ‘1’. |
Bit 24 – SCL SCL Line Value
| Value | Description |
|---|---|
| 0 | SCL line sampled value is ‘0’. |
| 1 | SCL line sampled value is ‘1.’ |
Bit 23 – TXFLOCK Transmit FIFO Lock
| Value | Description |
|---|---|
| 0 | The Transmit FIFO is not locked. |
| 1 | The Transmit FIFO is locked. |
Bit 21 – SMBHHM SMBus Host Header Address Match (cleared on read)
| Value | Description |
|---|---|
| 0 | No SMBus Host Header Address received. |
| 1 |
A SMBus Host Header Address was received. |
Bit 20 – SMBDAM SMBus Default Address Match (cleared on read)
| Value | Description |
|---|---|
| 0 | No SMBus Default Address received. |
| 1 | A SMBus Default Address was received. |
Bit 19 – PECERR PEC Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No SMBus PEC error occurred. |
| 1 | A SMBus PEC error occurred. |
Bit 18 – TOUT Timeout Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No SMBus timeout occurred. |
| 1 | SMBus timeout occurred. |
Bit 17 – SMBAF SMBus Alert Flag (cleared on read)
| Value | Description |
|---|---|
| 0 |
No SMBus client drives the SMBALERT line. |
| 1 |
At least one SMBus client drives the SMBALERT line. |
Bit 16 – MCACK Host Code Acknowledge (cleared on read)
MACK used in Client mode:
| Value | Description |
|---|---|
| 0 | No host code has been received. |
| 1 | A host code has been received. |
Bit 11 – EOSACC End Of Client Access (cleared on read)
This bit is only used in Client mode.
EOSACC behavior can be seen in figures Repeated Start and Reversal from Read Mode to Write Mode and Repeated Start and Reversal from Write Mode to Read Mode.
| Value | Description |
|---|---|
| 0 | A Client Access is being performed. |
| 1 | Client Access is finished. End Of Client Access is automatically set as soon as SVACC is reset. |
Bit 10 – SCLWS Clock Wait State
This bit is only used in Client mode.
SCLWS behavior can be seen in figures Clock Stretching in Read Mode and Clock Stretching in Write Mode.
| Value | Description |
|---|---|
| 0 | The clock is not stretched. |
| 1 | The clock is stretched. FLEX_TWI_THR / FLEX_TWI_RHR buffer is not filled / emptied before the transmission / reception of a new character. |
Bit 9 – ARBLST Arbitration Lost (cleared on read)
This bit is only used in Host mode.
| Value | Description |
|---|---|
| 0 | Arbitration won. |
| 1 | Arbitration lost. Another host of the TWI bus has won the multi-host arbitration. TXCOMP is set at the same time. |
Bit 8 – NACK Not Acknowledged (cleared on read)
NACK used in Host mode:
0: Each data byte has been correctly received by the far-end side TWI client component.
1: A data or address byte has not been acknowledged by the client component. Set at the same time as TXCOMP.
NACK used in Client Read mode:
0: Each data byte has been correctly received by the host.
1: In Read mode, a data byte has not been acknowledged by the host. When NACK is set the user must not fill FLEX_TWI_THR even if TXRDY is set, because it means that the host will stop the data transfer or re initiate it.
Note that in Client Write mode all data are acknowledged by the TWI.
Bit 7 – UNRE Underrun Error (cleared on read)
This bit is only used in Client mode if clock stretching is disabled.
| Value | Description |
|---|---|
| 0 | FLEX_TWI_THR has been filled on time. |
| 1 | FLEX_TWI_THR has not been filled on time. |
Bit 6 – OVRE Overrun Error (cleared on read)
This bit is only used in Client mode if clock stretching is disabled.
| Value | Description |
|---|---|
| 0 | FLEX_TWI_RHR has not been loaded while RXRDY was set. |
| 1 | FLEX_TWI_RHR has been loaded while RXRDY was set. Reset by read in FLEX_TWI_SR when TXCOMP is set. |
Bit 5 – GACC General Call Access (cleared on read)
This bit is only used in Client mode.
GACC behavior can be seen in figure Host Performs a General Call.
| Value | Description |
|---|---|
| 0 | No general call has been detected. |
| 1 | A general call has been detected. After the detection of general call, if need be, the user may acknowledge this access and decode the following bytes and respond according to the value of the bytes. |
Bit 4 – SVACC Client Access
This bit is only used in Client mode.
SVACC behavior can be seen in figures Read Access Ordered by a Host, Write Access Ordered by a Host, Repeated Start and Reversal from Read Mode to Write Mode and Repeated Start and Reversal from Write Mode to Read Mode.
| Value | Description |
|---|---|
| 0 | TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected. |
| 1 | Indicates that the address decoding sequence has matched (a host has sent SADR). SVACC remains high until a NACK or a STOP condition is detected. |
Bit 3 – SVREAD Client Read
This bit is only used in Client mode. When SVACC is low (no client access has been detected) SVREAD is irrelevant.
SVREAD behavior can be seen in figures Read Access Ordered by a Host, Write Access Ordered by a Host, Repeated Start and Reversal from Read Mode to Write Mode and Repeated Start and Reversal from Write Mode to Read Mode.
| Value | Description |
|---|---|
| 0 | Indicates that a write access is performed by a host. |
| 1 | Indicates that a read access is performed by a host. |
Bit 2 – TXRDY Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)
TXRDY used in Host mode:
0: The transmit holding register has not been transferred into the internal shifter. Set to 0 when writing into FLEX_TWI_THR.
1: As soon as a data byte is transferred from FLEX_TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enables TWI).
TXRDY behavior in Host mode can be seen in figures Host Write with One Data Byte,Host Write with Multiple Data Bytes and Host Write with One Byte Internal Address and Multiple Data Bytes.
TXRDY used in Client mode:
0: As soon as data is written in FLEX_TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK).
1: Indicates that FLEX_TWI_THR is empty and that data has been transmitted and acknowledged.
If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the user must not fill FLEX_TWI_THR to avoid losing it.
TXRDY behavior in Client mode can be seen in figures Read Access Ordered by a Host, Clock Stretching in Read Mode, Repeated Start and Reversal from Read Mode to Write Mode and Repeated Start and Reversal from Write Mode to Read Mode.
When FIFOs are enabled:
0: Transmit FIFO is full and cannot accept more data.
1: Transmit FIFO is not full; one or more data can be written according to TXRDYM field configuration.
TXRDY behavior with FIFOs enabled is illustrated in TXRDY and RXRDY Behavior.
Bit 1 – RXRDY Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)
When FIFOs are disabled:
0: No character has been received since the last FLEX_TWI_RHR read operation.
1: A byte has been received in FLEX_TWI_RHR since the last read.
RXRDY behavior in Host mode can be seen in figure Host Read with Multiple Data Bytes.
RXRDY behavior in Client mode can be seen in figures Write Access Ordered by a Host, Clock Stretching in Write Mode, Repeated Start and Reversal from Read Mode to Write Mode and Repeated Start and Reversal from Write Mode to Read Mode.
When FIFOs are enabled:
0: Receive FIFO is empty; no data to read.
1: At least one unread data is in the Receive FIFO.
RXRDY behavior with FIFO enabled is illustrated in TXRDY and RXRDY Behavior.
Bit 0 – TXCOMP Transmission Completed (cleared by writing FLEX_TWI_THR)
TXCOMP used in Host mode:
0: During the length of the current frame.
1: When both holding register and internal shifter are empty and STOP condition has been sent.
TXCOMP behavior in Host mode can be seen in figures Host Write with One Byte Internal Address and Multiple Data Bytes and Host Read with Multiple Data Bytes.
TXCOMP used in Client mode:
0: As soon as a Start is detected.
1: After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Client mode can be seen in figures Clock Stretching in Read Mode, Clock Stretching in Write Mode, Repeated Start and Reversal from Read Mode to Write Mode and Repeated Start and Reversal from Write Mode to Read Mode.