63.10.12 USART Channel Status Register (Default Mode)
For LIN-specific configurations, see USART Channel Status Register (LIN_MODE).
| Name: | FLEX_US_CSR (DEFAULT_MODE) |
| Offset: | 0x214 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| MANE | |||||||||
| Access | R | ||||||||
| Reset | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CTS | CMP | CTSIC | |||||||
| Access | R | R | R | ||||||
| Reset | – | – | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| NACK | ITER | TXEMPTY | TIMEOUT | ||||||
| Access | R | R | R | R | |||||
| Reset | – | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PARE | FRAME | OVRE | RXBRK | TXRDY | RXRDY | ||||
| Access | R | R | R | R | R | R | |||
| Reset | – | – | – | – | – | – |
Bit 24 – MANE Manchester Error
| Value | Description |
|---|---|
| 0 | No Manchester error has been detected since the last RSTSTA command was issued. |
| 1 | At least one Manchester error has been detected since the last RSTSTA command was issued. |
Bit 23 – CTS Image of CTS Input
| Value | Description |
|---|---|
| 0 | CTS input is driven low. |
| 1 | CTS input is driven high. |
Bit 22 – CMP Comparison Status
| Value | Description |
|---|---|
| 0 | No received character matched the comparison criteria programmed in VAL1, VAL2 fields and CMPPAR bit in since the last RSTSTA command was issued. |
| 1 | A received character matched the comparison criteria since the last RSTSTA command was issued. |
Bit 19 – CTSIC Clear to Send Input Change Flag
| Value | Description |
|---|---|
| 0 | No input change has been detected on the CTS pin since the last read of FLEX_US_CSR. |
| 1 | At least one input change has been detected on the CTS pin since the last read of FLEX_US_CSR. |
Bit 13 – NACK Non Acknowledge Interrupt
| Value | Description |
|---|---|
| 0 | Non acknowledge has not been detected since the last RSTNACK. |
| 1 | At least one non acknowledge has been detected since the last RSTNACK. |
Bit 10 – ITER Max Number of Repetitions Reached
| Value | Description |
|---|---|
| 0 | Maximum number of repetitions has not been reached since the last RSTIT command was issued. |
| 1 | Maximum number of repetitions has been reached since the last RSTIT command was issued. |
Bit 9 – TXEMPTY Transmitter Empty (cleared by writing FLEX_US_THR)
| Value | Description |
|---|---|
| 0 | There are characters in either FLEX_US_THR or the Transmit Shift Register, or the transmitter is disabled. |
| 1 | There are no characters in FLEX_US_THR, nor in the Transmit Shift Register. |
Bit 8 – TIMEOUT Receiver Timeout
| Value | Description |
|---|---|
| 0 | There has not been a timeout since the last Start Timeout command (FLEX_US_CR.STTTO) or the Timeout Register is 0. |
| 1 | There has been a timeout since the last Start Timeout command (FLEX_US_CR.STTTO). |
Bit 7 – PARE Parity Error
| Value | Description |
|---|---|
| 0 | No parity error has been detected since the last RSTSTA command was issued. |
| 1 | At least one parity error has been detected since the last RSTSTA command was issued. |
Bit 6 – FRAME Framing Error
| Value | Description |
|---|---|
| 0 | No stop bit has been detected low since the last RSTSTA command was issued. |
| 1 | At least one stop bit has been detected low since the last RSTSTA command was issued. |
Bit 5 – OVRE Overrun Error
| Value | Description |
|---|---|
| 0 | No overrun error has occurred since the last RSTSTA command was issued. |
| 1 | At least one overrun error has occurred since the last RSTSTA command was issued. |
Bit 2 – RXBRK Break Received/End of Break
| Value | Description |
|---|---|
| 0 | No break received or end of break detected since the last RSTSTA command was issued. |
| 1 | Break received or end of break detected since the last RSTSTA command was issued. |
Bit 1 – TXRDY Transmitter Ready (cleared by writing FLEX_US_THR)
When FIFOs are disabled:
0: A character in FLEX_US_THR is waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
1: There is no character in FLEX_US_THR.
When FIFOs are enabled:
0: Transmit FIFO is full and cannot accept more data.
1: Transmit FIFO is not full; one or more data can be written according to TXRDYM field configuration.
TXRDY behavior with FIFO enabled is illustrated in 63.7.11.5 TXEMPTY, TXRDY and RXRDY Behavior.
Bit 0 – RXRDY Receiver Ready (cleared by reading FLEX_US_RHR)
When FIFOs are disabled:
0: No complete character has been received since the last read of FLEX_US_RHR or the receiver is disabled. If characters were received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1: At least one complete character has been received and FLEX_US_RHR has not yet been read.
When FIFOs are enabled:
0: Receive FIFO is empty; no data to read
1: At least one unread data is in the Receive FIFO
RXRDY behavior with FIFO enabled is illustrated in 63.7.11.5 TXEMPTY, TXRDY and RXRDY Behavior.