63.10.6 USART Interrupt Enable Register (Default Mode)

For LIN-specific configurations, see USART Interrupt Enable Register (LIN_MODE).

This register can only be written if the WPITEN bit is cleared in the USART Write Protection Mode Register.

The following configuration values are valid for all listed bit names of this register:

0: No effect

1: Enables the corresponding interrupt.

Name: FLEX_US_IER (DEFAULT_MODE)
Offset: 0x208
Reset: 
Property: Write-only

Bit 3130292827262524 
        MANE 
Access W 
Reset  
Bit 2322212019181716 
  CMP  CTSIC    
Access WW 
Reset  
Bit 15141312111098 
   NACK  ITERTXEMPTYTIMEOUT 
Access WWWW 
Reset  
Bit 76543210 
 PAREFRAMEOVRE  RXBRKTXRDYRXRDY 
Access WWWWWW 
Reset  

Bit 24 – MANE Manchester Error Interrupt Enable

Bit 22 – CMP Comparison Interrupt Enable

Bit 19 – CTSIC Clear to Send Input Change Interrupt Enable

Bit 13 – NACK Non Acknowledge Interrupt Enable

Bit 10 – ITER Max number of Repetitions Reached Interrupt Enable

Bit 9 – TXEMPTY TXEMPTY Interrupt Enable

Bit 8 – TIMEOUT Timeout Interrupt Enable

Bit 7 – PARE Parity Error Interrupt Enable

Bit 6 – FRAME Framing Error Interrupt Enable

Bit 5 – OVRE Overrun Error Interrupt Enable

Bit 2 – RXBRK Receiver Break Interrupt Enable

Bit 1 – TXRDY TXRDY Interrupt Enable

Bit 0 – RXRDY RXRDY Interrupt Enable